Tecnologo

PROCESSOR BOARD (VIDEO CONTROLLER) WITH TELL TALE SCHEMATIC
4 3 2
REV
EG A

757-044-10
1
ECO
12104 BOM CHANGES PRODUCTION RELEASE

REV A

PAGE 1 OF 24

REVISIONS DESCRIPTION

BY/DATE
KRK/22APR04 KRK/08MAY04

CHK/DATE
-

BUS CONTROLLER

D

DEVICE SELECTS

SRAM 4MB .5M X 32 X 2

RTC 1

D
MEMORY CARD

CYCLE TIMING

SA [31:0] ADDR LATCH BOOT ROM GAME 960KA PIXELCG MEMORY BOARD CONNS DATA BUFF/ LATCH DATA STEERING SD [31:0] AUDIO MEM

CLOCKS & RESETS

POWER SUPPLIES POWER MONITOR & WATCHDOG 5V,3.3V,1.5V,1.8V, 2.5V,5VA,12VA BATTERY AND CHARGER CG MEMORY SIGNALS CGBL0:15 CGBK0:15

C

C

AUDIO MEMORY BUS YAA0:23 YD0:7

SHT 2 960 CPU AND 5V TO 3V TRANSLATION
TELL TALE

SRAM ENABLE SDRAM

SHT 3 CLOCK GENERATOR SHT 4 BUS CONTROLLER SHT 5 BUSTERMINATORS SHT 6 BIT GRAPHICS FPGA SHT 7 GRAPHICS SDRAM SHT 8 VIDEO DAC B SHT 9 SRAM

DOOR SECURITY CPLD

DOOR STATUS

32/64MB

BIT BLITZ

32MB SDRAM 1M X 32

BATTERY LOW DSPA0:23 DSPD16:47

AUDIO CPLD R,G,B [7:0]

AUDIO CPLD

VIDEO DAC AMP TRUE COLOR DAC AUDIO OUT L&R AMP AUX IN L&R VOLCTL ADC DIGITAL AUDIO

B
DWG_NO

SHT 10 SERIAL FPGA SHT 11 SERIAL TRANSCEIVERS SHT 12 SENETDRIVERS
SERIAL PORTS R,G,B,H&VSYNV M/B MOTHERBOARD

757 044 10

CONNS

SHT 13 MEMORY MEZANNINE CONNECTORS
SERIAL FPGA SENET 1 & 2

SHT 14 MOTHERBOARD CONNECTORS
I2C

SHT 15 DC-DC CONVERTERS SHT 16 BATTERY BACKUP
OPTION OPTION CARD

STATUS LEDS QUART 1&2 SENET 1&2 I2C 1&2 SERIAL VOL CTL

LEDS

RTC 2 CARD CONN

SHT 17 POWER MONITOR/ RESET SHT 18 TELL TALE A SHT 19 RTC SHT 20AUDIO CPLD, SDRAM SHT 21 AUDIO DSP SHT 22 AUDIO ADC SHT 23 AUDIO DAC SHT 24 OPTION MEZANNINE CONNECTOR 4 3

A
ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY OTHERS IN PART OR IN WHOLE,WITHOUT THE EXPRESS CONSENT OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
DRAWN DATE CHECKED DATE

INTERNATIONAL GAME TECHNOLOGY
R

9295 PROTOTYPE DRIVE RENO NV 89521

TITLE

PCB,GK ENHANCED CTL SCH
DWG_SIZE DWG_NO REV_LTR

C
APPROVED

757 044 10
DATE SCALE

A
SHT 1 OF24

KRK

20JUN03

NONE

2

1

JULY 29, 2005

ELECTRONIC DIAGRAMS & PARTS: GAME KING 19” UPRIGHT (821-352-01)

31

PROCESSOR BOARD (VIDEO CONTROLLER) WITH TELL TALE SCHEMATIC

757-044-10

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PAGE 2 OF 24

4

3

2

1

5V
SD[0:31]

C344 0.1UF 25V

1 2

C203 0.1UF 25V

1 2

C184 0.1UF 25V

1 2

C181 0.1UF 25V

1 2

C190 0.1UF 25V

1 2C186 0.1UF 25V

5,6,9,10,13,20,24
1

LAD[0:31]
2

3.3V C195 0.1UF
1 2

3.3V

C329 0.1UF 25V

1 2

C178 0.1UF 25V

1 2

C232 0.1UF 25V

1 2

C183 0.1UF 25V

1 2

C187 0.1UF 25V

1 2

1 2

C144 6.8UF 16V 7 22 35 50 U89 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 1DIR 2DIR 1SAB 2SAB 1SBA 2SBA 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 1 28 3 2654 31
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 LAD16 LAD17 LAD18 LAD19 LAD20 LAD21 LAD22 LAD23 LAD24 LAD25 LAD26 LAD27 LAD28 LAD29 LAD30 LAD31

7 22 35 50

D

25V

3.3V U93 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 1DIR 2DIR 1SAB 2SAB 1SBA 2SBA 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 1 28 3 26 54 31
SD16 SD17 SD18 SD19 SD20 SD21SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31
1 2

D
C330 0.1UF 25V
1 2

5V 5V U87

LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15

5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 56 29 2 27 55 30

1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 1OE 2OE

5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 56 29 2 27 55 30

VCC1...