Trabajjitos Importantes

74HC00; 74HCT00
Quad 2-input NAND gate
Rev. 6 — 14 December 2011

Product data sheet

1. General description
The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC00; 74HCT00 provides a quad 2-input NAND function.

2. Features and benefits
 Input levels:
 For 74HC00: CMOSlevel
 For 74HCT00: TTL level
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
 Multiple package options
 Specified from 40 C to +85 C and from 40 C to +125 C

3. Ordering information
Table 1.

Ordering information

Type number

Package
Temperature range

74HC00N

Name

Description

Version

40 C to +125 C

DIP14plastic dual in-line package; 14 leads (300 mil)

SOT27-1

40 C to +125 C

SO14

plastic small outline package; 14 leads; body width
3.9 mm

SOT108-1

40 C to +125 C

SSOP14

plastic shrink small outline package; 14 leads; body
width 5.3 mm

SOT337-1

40 C to +125 C

TSSOP14

plastic thin shrink small outline package; 14 leads;
body width 4.4 mm

SOT402-1

40 Cto +125 C

DHVQFN14

plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5  3  0.85 mm

74HCT00N
74HC00D
74HCT00D
74HC00DB
74HCT00DB
74HC00PW
74HCT00PW
74HC00BQ
74HCT00BQ

74HC00; 74HCT00

NXP Semiconductors

Quad 2-input NAND gate

4. Functional diagram
1
1 1A
2 1B

1Y 3

4 2A
5 2B

2Y 6

93A
10 3B

3Y 8

12 4A
13 4B

4Y 11

2
4
5
9
10
12
13

&

3

&

6

&

8
A
Y

11

&

B
mna212

Fig 1.

mna211

mna246

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram (one gate)

5. Pinning information
5.1 Pinning

74HC00
74HCT00

1

1A

terminal 1
index area

1Y

13 4B

13 4B

3

12 4A

4

11 4Y

1Y

312 4A

2A

2A

4

11 4Y

2B

5

2B

5

10 3B

2Y

6

2Y

6

9

3A

8

2

2

GND

7

8

3Y

3Y

1B

1B

14 VCC

7

1

GND

1A

14 VCC

74HC00
74HCT00

GND(1)

10 3B
9

3A

001aal324

Transparent top view

001aal323

(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attachmaterial. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.

Fig 4.

Pin configuration DIP14, SO14 and (T)SSOP14

Fig 5.

Pin configuration DHVQFN14

5.2 Pin description
Table 2.

Pin description

Symbol

Pin

Description

1A to 4A

1, 4, 9, 12

data input

1B to4B

2, 5, 10, 13

data input

74HC_HCT00

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 14 December 2011

© NXP B.V. 2011. All rights reserved.

2 of 16

74HC00; 74HCT00

NXP Semiconductors

Quad 2-input NAND gate

Table 2.

Pin description …continued

Symbol

Pin

Description

1Y to 4Y

3, 6, 8, 11data output

GND

7

ground (0 V)

VCC

14

supply voltage

6. Functional description
Table 3.

Function table[1]

Input

Output

nA

nB

nY

L

X

H

X

L

H

H

H

L

[1]

H = HIGH voltage level; L = LOW voltage level; X = don’t care.

7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC60134). Voltages are referenced to GND (ground = 0 V).
Symbol

Parameter

VCC

supply voltage

IIK

input clamping current

VI < 0.5 V or VI > VCC + 0.5 V

IOK

output clamping current

VO < 0.5 V or VO > VCC + 0.5 V

IO

output current

0.5 V < VO < VCC + 0.5 V

-

25

mA

ICC

supply current

-

50

mA

IGND

ground current

50

-

mA

Tstg...