Atmega 8515

Features
• High-performance, Low-power AVR® 8-bit Microcontroller • RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 8K Bytes of In-System Self-programmable Flash Endurance: 10,000Write/Erase Cycles – Optional Boot Code Section with Independent Lock bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 512 Bytes Internal SRAM – Up to 64K Bytes Optional External Memory Space – Programming Lock for Software Security Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler and CompareMode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Three PWM Channels – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External andInternal Interrupt Sources – Three Sleep Modes: Idle, Power-down and Standby I/O and Packages – 35 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad QFN/MLF Operating Voltages – 2.7 - 5.5V for ATmega8515L – 4.5 - 5.5V for ATmega8515 Speed Grades – 0 - 8 MHz for ATmega8515L – 0 - 16 MHz for ATmega8515

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8-bit Microcontroller with 8K Bytes In-SystemProgrammable Flash ATmega8515 ATmega8515L

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2512K–AVR–01/10

Pin Configurations
Figure 1. Pinout ATmega8515
PDIP
(OC0/T0) PB0 (T1) PB1 (AIN0) PB2 (AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD) PD0 (TDX) PD1 (INT0) PD2 (INT1) PD3 (XCK) PD4 (OC1A) PD5 (WR) PD6 (RD) PD7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 2827 26 25 24 23 22 21 VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE0 (ICP/INT2) PE1 (ALE) PE2 (OC1B) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8)

TQFP/MLF
PB4 (SS) PB3 (AIN1) PB2 (AIN0) PB1 (T1) PB0 (OC0/T0) NC* VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) PA3 (AD3)

PLCC
PB4 (SS) PB3 (AIN1) PB2 (AIN0) PB1 (T1) PB0 (OC0/T0) NC*VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) PA3 (AD3)
NOTES: 1. MLF bottom pad should be soldered to ground. 2. * NC = Do not connect (May be used in future devices)

44 43 42 41 40 39 38 37 36 35 34

12 13 14 15 16 17 18 19 20 21 22

2

ATmega8515(L)
2512K–AVR–01/10

(WR) PD6 (RD) PD7 XTAL2 XTAL1 GND NC* (A8) PC0 (A9) PC1 (A10) PC2 (A11) PC3 (A12) PC4

(WR) PD6 (RD) PD7 XTAL2 XTAL1 GND NC*(A8) PC0 (A9) PC1 (A10) PC2 (A11) PC3 (A12) PC4

18 19 20 21 22 23 24 25 26 27 28

(MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD) PD0 NC* (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK) PD4 (OC1A) PD5

1 2 3 4 5 6 7 8 9 10 11

33 32 31 30 29 28 27 26 25 24 23

PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE0 (ICP/INT2) NC* PE1 (ALE) PE2 (OC1B) PC7 (A15) PC6 (A14) PC5 (A13)

(MOSI) PB5 (MISO) PB6 (SCK) PB7RESET (RXD) PD0 NC* (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK) PD4 (OC1A) PD5

7 8 9 10 11 12 13 14 15 16 17

6 5 4 3 2 1 44 43 42 41 40

39 38 37 36 35 34 33 32 31 30 29

PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE0 (ICP/INT2) NC* PE1 (ALE) PE2 (OC1B) PC7 (A15) PC6 (A14) PC5 (A13)

ATmega8515(L)
Overview
The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR enhancedRISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2. Block Diagram
PA0 - PA7 VCC PE0 - PE2 PC0 - PC7

Block Diagram

PORTA DRIVERS/BUFFERS

PORTE DRIVERS/ BUFFERS

PORTC DRIVERS/BUFFERS

GND

PORTA...