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The Memory block holds and delays its input by one integration time step. This block accepts and outputs continuous signals. The block accepts one input and generates one output. Each signal can be scalar or vector. If the input is a vector, the block holds and delays all elements of the vector by the same time step.
You specify the block output for the first time step with the Initial conditionparameter. Careful selection of this parameter can minimize unwanted output behavior. However, you cannot specify the sample time. This block can only inherit the sample time from the driving block or the solver used for the entire model. For more information, see the description for the Inherit sample time parameter.
Tip   Avoid using the Memory block when: * Your model uses thevariable-step solver ode15s or ode113. * The input to the block changes during simulation. |
When the Memory block inherits a discrete sample time, the block is analogous to the Unit Delay block. However, the Memory block does not support state logging. If logging the final state is necessary, use a Unit Delay block instead.
Comparison with Similar Blocks
Blocks with Similar Functionality
The UnitDelay, Memory, and Zero-Order Hold blocks provide similar functionality but have different capabilities. Also, the purpose of each block is different. The sections that follow highlight some of these differences.
Recommended Usage for Each Block
Block | Purpose of the Block | Reference Examples |
Unit Delay | Implement a delay using a discrete sample time that you specify. Ideally, the blockaccepts and outputs signals with a discrete sample time. | * sldemo_enginewc (Compression subsystem) |
Memory | Implement a delay by one integration time step. Ideally, the block accepts and outputs signals where the sample time is continuous or fixed in minor time step. For more information, see Types of Sample Time in the Simulink documentation. | * sldemo_bounce * sldemo_clutch(Friction Mode Logic/Lockup FSM subsystem) |
Zero-Order Hold | Convert an input signal with a continuous sample time to an output signal with a discrete sample time. | * sldemo_radar_eml * aero_dap3dof |
Overview of Block Capabilities
Capability | Block |
| Unit Delay | Memory | Zero-Order Hold |
Specification of initial condition | Yes | Yes | No, because the block output at time t = 0must match the input value. |
Specification of sample time | Yes | No, because the block can only inherit sample time (from the driving block or the solver used for the entire model). | Yes |
Support for frame-based signals | Yes | No | Yes |
Support for state logging | Yes | No | No |
Effect of Solver Specification on Block Output
When you specify a discrete sample time in the dialog boxfor a Unit Delay or Zero-Order Hold block, the block output can differ depending on the solver specification for the model.
Suppose that you have a model with Unit Delay and Zero-Order Hold blocks, which both use a discrete sample time of 1:

The Repeating Sequence Stair block uses a continuous sample time of 0 to provide input signals to the Unit Delay and Zero-Order Hold blocks.
If themodel uses a fixed-step solver with a step size of 1, the scope shows the following simulation results:

If the model uses a variable-step solver, the scope shows the following simulation results:

The Zero-Order Hold block takes the input value of the Repeating Sequence Stair block at t = 0, 1, 2, ... , 9 and holds each input value for a sample period (1 second). The Unit Delay block applies thesame 1-second hold to each input value of the Repeating Sequence Stair block, but also delays each value by a sample period. The Initial conditions parameter specifies the output for the Unit Delay block during the first sample period. For more information about sample time, see What Is Sample Time? and Specify Sample Time.
Solver specification for a model also affects the behavior of the...