Analísis De Los Avances Científicos Que Aportará El Gran Colisonador De Hadrones Para La Física Moderna

Simulation of a VHDL code for a pipelined implementation of CORDIC
1. Copy the VHDL file Cordic.Vhd for CORDIC algorithm verification from
S:\TN\E\027_Digital_Kommunikationselektronik\CORDIC VHDLcode\ to
your own directory.
2. Create a new FPGA project by clicking on File » New » Project » FPGA
Project and rename the new project file by clicking on File » Save Project
As.
3. Add theVHDL file Cordic.Vhd to the project by right clicking the project file
name in the Projects panel and selecting Add Existing to Project ….
4. Open Cordic.Vhd by double clicking the file nameCordic.Vhd.
5. Click on Design » Create VHDL Testbench. A testbench
Test_cordic.VHDTST is created and opened as follows.
------------------------------------------------------------- VHDL Testbench forcordic
-- 2006 10 23 11 57 33
-- Created by "EditVHDL"
-- "Copyright (c) 2002 Altium Limited"
-----------------------------------------------------------Library IEEE;
Use
IEEE.std_logic_1164.all;Use
IEEE.std_logic_textio.all;
Use
STD.textio.all;
----------------------------------------------------------------------------------------------------------------------entity Testcordic is
endTestcordic;
----------------------------------------------------------------------------------------------------------------------architecture stimulus of Testcordic is
file RESULTS: TEXT openWRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
angle: std_logic_vector(7 downto 0);
clk: std_logic;
datax: std_logic_vector(11 downto 0);
datay: std_logic_vector(11 downto 0);
res:std_logic;
x_n: std_logic_vector(11 downto 0);
y_n: std_logic_vector(11 downto 0)
) is
variable l_out : line;
begin
write(l_out, now, right, 15);
write(l_out, angle, right, 9);
write(l_out, clk,right, 2);
write(l_out, datax, right, 13);
write(l_out, datay, right, 13);
write(l_out, res, right, 2);
write(l_out, x_n, right, 13);
write(l_out, y_n, right, 13);
writeline(RESULTS, l_out);
end...