Flip-Flop-Jk

HD74LS73A
Dual J-K Flip-Flops (with Clear)
REJ03D0414–0300 Rev.3.00 Jul.22.2005

Features
• Ordering Information
Part Name HD74LS73AP HD74LS73ARPEL Package Type DILP-14 pin SOP-14 pin (JEDEC) Package Code (Previous Code) PRDP0014AB-B (DP-14AV) Package Abbreviation P Taping Abbreviation (Quantity) — EL (2,500 pcs/reel)

PRSP0014DE-A RP (FP-14DNV) Note: Please consult the sales office forthe above package availability.

Pin Arrangement

1CK 1CLR 1K VCC 2CK 2CLR 2J

1 2 3 4 5 6 7 K J

CLR Q Q Q Q CLR CK K

14 13 12 11 10 9 8

1J 1Q 1Q GND 2K 2Q 2Q

CK J

(Top view)

Function Table
Inputs Clear L H H H H H Clock X ↓ ↓ ↓ ↓ H J X L H L H X K X L L H H X Q L Q0 H L Toggle QO QO Outputs Q H Q0 L H

H; high level, L; low level, X; irrelevant, ↓; transition from highto low level, Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established. Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓.

Rev.3.00, Jul.22.2005, page 1 of 6

HD74LS73A

Block Diagram (1/2)

Q

QClear

K

J

Clock

Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 –65 to +150 Unit V V mW °C

Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.

Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Clock frequency Pulsewidth Setup time Hold time Symbol VCC IOH IOL Topr fclock tw (Clock High) tw (Clear Low) tsu (“H” Data) tsu (“L” Data) th Min 4.75 — — –20 0 20 25 20↓ 20↓ 0↓ Typ 5.00 — — 25 — — — — — — Max 5.25 –400 8 75 30 — — — — — Unit V µA mA °C MHz ns ns ns

Note: ↓; The arrow indicates the falling edge.

Rev.3.00, Jul.22.2005, page 2 of 6

HD74LS73A

Electrical Characteristics
(Ta = –20 to +75 °C)Item Input voltage Symbol VIH VIL VOH Output voltage VOL J, K Clear Clock J, K Input current Clear Clock J, K Clear Clock Short-circuit output current Supply current** Input clamp voltage IIL min. 2.0 — 2.7 — — — — — — — — — — — –20 — — typ.* — — — — — — — — — — — — — — — 4 — max. — 0.8 — 0.5 0.4 20 60 80 –0.4 –0.8 –0.8 0.1 0.3 0.4 –100 6 –1.5 mA VCC = 5.25 V, VI = 0.4 V Unit V V V V VCC = 4.75 V,VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 8 mA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V Condition

IIH

µA

VCC = 5.25 V, VI = 2.7 V

II IOS ICC VIK

mA mA mA V

VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA

Notes: * VCC = 5 V, Ta = 25°C ** With all outputs open, ICC is measured with the Q and Q outputs high in turn. At time of measurement, theclock input is founded.

Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item Maximum clock frequency Propagation delay time Symbol fmax tPLH tPHL Inputs Clear Clock Outputs Q, Q min. 30 — — typ. 45 15 15 max. — 20 20 Unit MHz ns ns Condition CL = 15 pF, RL = 2 kΩ

Timing Definition
tw 3V 1.3 V Clock tsu th tsu th 1.3 V 1.3 V 0V 3V 1.3 V J, K "H" Data "L" Data 1.3 V 1.3 V 0V

Rev.3.00,Jul.22.2005, page 3 of 6

HD74LS73A

Testing Method
Test Circuit 1. ƒmax, tPLH, tPHL, (Clock→Q, Q)
VCC Input 4.5V RL J P.G. Zout=50Ω CK K CLR Q Same as Load Circuit 1. Q CL Output Q Load circuit 1 Output Q

Notes:

1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H).

2. tPHL (Clear→Q), tPLH (Clear→Q)
VCC 4.5V Input J P.G.Zout=50Ω Input CK K CLR P.G. Zout=50Ω Q Same as Load Circuit 1. Q CL Output Q RL Load circuit 1 Output Q

Notes:

1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H).

Rev.3.00, Jul.22.2005, page 4 of 6

HD74LS73A Waveforms 1
tTLH tTHL tw(L) 1.3 V 10% tPLH 1.3 V Q tPHL tPLH tPHL VOH 1.3 V VOL 1.3 V 0V 3V

Clock

10%

90% 90%...