Mc9S08Ac60
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Publicado: 19 de julio de 2011
MC9S08AC60 MC9S08AC48 MC9S08AC32
Data Sheet
HCS08 Microcontrollers
MC9S08AC60 Rev. 2 3/2008
freescale.com
MC9S08AC60 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
• • • • • • 40-MHz HCS08 CPU (central processor unit) 20-MHz internal bus frequency HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpointsetting during in-circuit debugging (plus two more breakpoints in on-chip debug module) On-chip in-circuit emulator (ICE) Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Supports both tag and force breakpoints. Support for up to 32 interrupt/reset sources Up to 60 KB of on-chip FLASH memory with securityoptions Up to 2 KB of on-chip RAM Clock source options include crystal, resonator, external clock, or internally generated clock with precision NVM trimming using ICG module Optional watchdog computer operating properly (COP) reset with option to run from independent 1kHz internal clock source or bus clock Low-voltage detection with reset or interrupt Illegal opcode detection with reset CyclicRedundancy Check (CRC) Module to support fast cyclic redundancy checks on memory. Wait plus two stops
Peripherals
• • ADC — Up to 16-channel, 10-bit analog-to-digital converter with automatic compare function SCI — Two serial communications interface modules with optional 13-bit break. supports LIN 2.0 Protocol and SAE J2602; Master extended break generation; Slave extended break detection SPI —Serial peripheral interface module IIC — Inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; capable of higher baudrates with reduced loading. 10-bit address extension option. Timers — Up to two 2-channel and one 6-channel 16-bit timer/pulse-width modulator (TPM) module: Selectable input capture, output compare, and edge-aligned PWM capability on each channel.Each timer module may be configured for buffered, centered PWM (CPWM) on all channels KBI — Up to 8-pin keyboard interrupt module CRC - Hardware CRC generation using a 16-bit shift register Up to 54 general-purpose input/output (I/O) pins Software selectable pullups on ports when used as inputs Software selectable slew rate control on ports when used as outputs Software selectable drive strength onports when used as outputs Master reset pin and power-on reset (POR) Internal pullup on RESET, IRQ, and BKGD/MS pins to reduce customer system cost 64-pin quad flat package (QFP) 64-pin low-profile quad flat package (LQFP) 48-pin quad flat pack no lead package (QFN) 44-pin low-profile quad flat package (LQFP) 32-pin low-profile quad flat package (LQFP)
Development Support
• •
•
• • • •
MemoryOptions
• •
Clock Source Options
Input/Output
• • • • • •
System Protection
• • • •
Package Options
• • • • •
Power-Saving Modes
•
MC9S08AC60 Series Data Sheet
Covers MC9S08AC60 MC9S08AC48 MC9S08AC32
MC9S08AC60 Series Rev. 2 3/2008
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the mostcurrent. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/
The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision Number 1 2
Revision Date 2/2008 3/2008 Market Launch Release.Description of Changes Preliminary customer release.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2008. All rights reserved. MC9S08AC60 Series Data Sheet, Rev. 2 6 Freescale Semiconductor
List of Chapters
Chapter Title Page
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9...
Data Sheet
HCS08 Microcontrollers
MC9S08AC60 Rev. 2 3/2008
freescale.com
MC9S08AC60 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
• • • • • • 40-MHz HCS08 CPU (central processor unit) 20-MHz internal bus frequency HC08 instruction set with added BGND instruction Background debugging system Breakpoint capability to allow single breakpointsetting during in-circuit debugging (plus two more breakpoints in on-chip debug module) On-chip in-circuit emulator (ICE) Debug module containing two comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Supports both tag and force breakpoints. Support for up to 32 interrupt/reset sources Up to 60 KB of on-chip FLASH memory with securityoptions Up to 2 KB of on-chip RAM Clock source options include crystal, resonator, external clock, or internally generated clock with precision NVM trimming using ICG module Optional watchdog computer operating properly (COP) reset with option to run from independent 1kHz internal clock source or bus clock Low-voltage detection with reset or interrupt Illegal opcode detection with reset CyclicRedundancy Check (CRC) Module to support fast cyclic redundancy checks on memory. Wait plus two stops
Peripherals
• • ADC — Up to 16-channel, 10-bit analog-to-digital converter with automatic compare function SCI — Two serial communications interface modules with optional 13-bit break. supports LIN 2.0 Protocol and SAE J2602; Master extended break generation; Slave extended break detection SPI —Serial peripheral interface module IIC — Inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; capable of higher baudrates with reduced loading. 10-bit address extension option. Timers — Up to two 2-channel and one 6-channel 16-bit timer/pulse-width modulator (TPM) module: Selectable input capture, output compare, and edge-aligned PWM capability on each channel.Each timer module may be configured for buffered, centered PWM (CPWM) on all channels KBI — Up to 8-pin keyboard interrupt module CRC - Hardware CRC generation using a 16-bit shift register Up to 54 general-purpose input/output (I/O) pins Software selectable pullups on ports when used as inputs Software selectable slew rate control on ports when used as outputs Software selectable drive strength onports when used as outputs Master reset pin and power-on reset (POR) Internal pullup on RESET, IRQ, and BKGD/MS pins to reduce customer system cost 64-pin quad flat package (QFP) 64-pin low-profile quad flat package (LQFP) 48-pin quad flat pack no lead package (QFN) 44-pin low-profile quad flat package (LQFP) 32-pin low-profile quad flat package (LQFP)
Development Support
• •
•
• • • •
MemoryOptions
• •
Clock Source Options
Input/Output
• • • • • •
System Protection
• • • •
Package Options
• • • • •
Power-Saving Modes
•
MC9S08AC60 Series Data Sheet
Covers MC9S08AC60 MC9S08AC48 MC9S08AC32
MC9S08AC60 Series Rev. 2 3/2008
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the mostcurrent. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/
The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision Number 1 2
Revision Date 2/2008 3/2008 Market Launch Release.Description of Changes Preliminary customer release.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2008. All rights reserved. MC9S08AC60 Series Data Sheet, Rev. 2 6 Freescale Semiconductor
List of Chapters
Chapter Title Page
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9...
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