Microcontroladores

Microcontroller Instruction Set
For interrupt response time information, refer to the hardware description chapter.

Instructions that Affect Flag Settings(1)
Instruction

Flag

Instruction

Flag

C

OV

AC

ADD

X

X

X

CLR C

O

ADDC

X

X

X

CPL C

X

SUBB

X

X

X

ANL C,bit

X

MUL

O

X

ANL C,/bit

X

DIV

O

X

ORLC,bit

X

DA

X

ORL C,/bit

X

RRC

X

MOV C,bit

X

RLC

X

CJNE

X

SETB C
Note:

C

OV

AC

Instruction Set

1

1. Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or
bits in the PSW) also affect flag settings.

The Instruction Set and Addressing Modes
Rn

Register R7-R0 of the currently selected Register Bank.

direct8-bit internal data location’s address. This could be an Internal Data RAM
location (0-127) or a SFR [i.e., I/O port, control register, status register, etc.
(128-255)].

@Ri

8-bit internal data RAM location (0-255) addressed indirectly through register
R1or R0.

#data

8-bit constant included in instruction.

#data 16

16-bit constant included in instruction.

addr 1616-bit destination address. Used by LCALL and LJMP A branch can be
.
anywhere within the 64K byte Program Memory address space.

addr 11

11-bit destination address. Used by ACALL and AJMP The branch will be
.
within the same 2K byte page of program memory as the first byte of the
following instruction.

rel

Signed (two’s complement) 8-bit offset byte. Used by SJMP and all
conditionaljumps. Range is -128 to +127 bytes relative to first byte of the
following instruction.

bit

Direct Addressed bit in Internal Data RAM or Special Function Register.

0509B-B–12/97

2-71

Instruction Set Summary
0

1

2

3

4

5

6

7

0

NOP

JBC
bit,rel
[3B, 2C]

JB
bit, rel
[3B, 2C]

JNB
bit, rel
[3B, 2C]

JC
rel
[2B, 2C]

JNC
rel
[2B, 2C]JZ
rel
[2B, 2C]

JNZ
rel
[2B, 2C]

1

AJMP
(P0)
[2B, 2C]

ACALL
(P0)
[2B, 2C]

AJMP
(P1)
[2B, 2C]

ACALL
(P1)
[2B, 2C]

AJMP
(P2)
[2B, 2C]

ACALL
(P2)
[2B, 2C]

AJMP
(P3)
[2B, 2C]

ACALL
(P3)
[2B, 2C]

2

LJMP
addr16
[3B, 2C]

LCALL
addr16
[3B, 2C]

RET
[2C]

RETI
[2C]

ORL
dir, A
[2B]

ANL
dir, A
[2B]

XRL
dir, a
[2B]

ORL
C,bit
[2B, 2C]

3

RR
A

RRC
A

RL
A

RLC
A

ORL
dir, #data
[3B, 2C]

ANL
dir, #data
[3B, 2C]

XRL
dir, #data
[3B, 2C]

JMP
@A + DPTR
[2C]

4

INC
A

DEC
A

ADD
A, #data
[2B]

ADDC
A, #data
[2B]

ORL
A, #data
[2B]

ANL
A, #data
[2B]

XRL
A, #data
[2B]

MOV
A, #data
[2B]

5

INC
dir
[2B]

DEC
dir
[2B]

ADD
A, dir
[2B]

ADDCA, dir
[2B]

ORL
A, dir
[2B]

ANL
A, dir
[2B]

XRL
A, dir
[2B]

MOV
dir, #data
[3B, 2C]

6

INC
@R0

DEC
@R0

ADD
A, @R0

ADDC
A, @R0

ORL
A, @R0

ANL
A, @R0

XRL
A, @R0

MOV
@R0, @data
[2B]

7

INC
@R1

DEC
@R1

ADD
A, @R1

ADDC
A, @R1

ORL
A, @R1

ANL
A, @R1

XRL
A, @R1

MOV
@R1, #data
[2B]

8

INC
R0

DEC
R0

ADDA, R0

ADDC
A, R0

ORL
A, R0

ANL
A, R0

XRL
A, R0

MOV
R0, #data
[2B]

9

INC
R1

DEC
R1

ADD
A, R1

ADDC
A, R1

ORL
A, R1

ANL
A, R1

XRL
A, R1

MOV
R1, #data
[2B]

A

INC
R2

DEC
R2

ADD
A, R2

ADDC
A, R2

ORL
A, R2

ANL
A, R2

XRL
A, R2

MOV
R2, #data
[2B]

B

INC
R3

DEC
R3

ADD
A, R3

ADDC
A, R3

ORL
A,R3

ANL
A, R3

XRL
A, R3

MOV
R3, #data
[2B]

C

INC
R4

DEC
R4

ADD
A, R4

ADDC
A, R4

ORL
A, R4

ANL
A, R4

XRL
A, R4

MOV
R4, #data
[2B]

D

INC
R5

DEC
R5

ADD
A, R5

ADDC
A, R5

ORL
A, R5

ANL
A, R5

XRL
A, R5

MOV
R5, #data
[2B]

E

INC
R6

DEC
R6

ADD
A, R6

ADDC
A, R6

ORL
A, R6

ANL
A, R6

XRL
A, R6...