Micros

PIC16F87XA
FIGURE 1-2: PIC16F874A/877A BLOCK DIAGRAM
13 Program Counter FLASH Program Memory 8 Level Stack (13-bit) RAM File Registers RAM Addr(1) 9 PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-VoltageProgramming 8 W reg PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE MCLR VDD, VSS RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS 3 MUX RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT

Program Bus

14 Instruction reg Direct Addr 7Addr MUX 8 Indirect Addr

FSR reg STATUS reg

8

ALU

Timer0

Timer1

Timer2

10-bit A/D

Parallel Slave Port

Data EEPROM

CCP1,2

Synchronous Serial Port

USART

Comparator

Voltage Reference

Device PIC16F874A PIC16F877A

Program FLASH 4K words 8K words

Data Memory 192 Bytes 368 Bytes

Data EEPROM 128 Bytes 256 Bytes

Note 1: Higher order bits are fromthe STATUS register.

© 2001 Microchip Technology Inc.

Advance Information

DS39582A-page 7

PIC16F87XA
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
There are three memory blocks in each of the PIC16F87XA devices. The Program Memory and Data Memory have separate buses so that concurrent access can occur and is detailed in this section. The EEPROM data memory block isdetailed in Section 3.0. Additional information on device memory may be found in the PICmicro™ Mid-Range Reference Manual (DS33023). The PIC16F87XA devices have a 13-bit program counter capable of addressing an 8K word x 14 bit program memory space. The PIC16F876A/877A devices have 8K words x 14 bits of FLASH program memory, while PIC16F873A/874A devices have 4K words x 14 bits. Accessing a locationabove the physically implemented address will cause a wraparound. The RESET vector is at 0000h and the interrupt vector is at 0004h.

FIGURE 2-1:

PIC16F876A/877A PROGRAM MEMORY MAP AND STACK
PC

FIGURE 2-2:

PIC16F873A/874A PROGRAM MEMORY MAP AND STACK
PC

CALL, RETURN RETFIE, RETLW

13

CALL, RETURN RETFIE, RETLW

13

Stack Level 1 Stack Level 2

Stack Level 1 Stack Level 2Stack Level 8

Stack Level 8

RESET Vector

0000h

RESET Vector

0000h

Interrupt Vector

0004h 0005h

Interrupt Vector

0004h 0005h

Page 0
07FFh 0800h

On-Chip Program Memory

Page 0
07FFh 0800h

Page 1 On-Chip Program Memory Page 2
17FFh 1800h 0FFFh 1000h

Page 1
0FFFh 1000h

Page 3
1FFFh 1FFFh

© 2001 Microchip Technology Inc.

Advance InformationDS39582A-page 13

PIC16F87XA
FIGURE 2-3: PIC16F876A/877A REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(1) TRISE(1) PCLATH INTCON PIE1 PIE2 PCON File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 80 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 General Purpose Register 80 Bytesaccesses 70h-7Fh Bank 2 Indirect addr.(*) TMR0 PCL STATUS FSR PORTB File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h...