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Features
• Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Data and Non-volatile Program and Data Memories – 2K Bytes of In-System Self Programmable Flash Endurance 10,000 Write/Erase Cycles – 128 Bytes In-SystemProgrammable EEPROM Endurance: 100,000 Write/Erase Cycles – 128 Bytes Internal SRAM – Programming Lock for Flash Program and EEPROM Data Security Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes – Four PWM Channels – On-chip Analog Comparator – Programmable Watchdog Timer with On-chipOscillator – USI – Universal Serial Interface – Full Duplex USART Special Microcontroller Features – debugWIRE On-chip Debugging – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low-power Idle, Power-down, and Standby Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator I/O and Packages – 18 Programmable I/OLines – 20-pin PDIP, 20-pin SOIC, and 32-pin MLF Operating Voltages – 1.8 - 5.5V (ATtiny2313) Speed Grades – ATtiny2313V: 0 - 2 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.4 - 5.5V – ATtiny2313: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V Power Consumption Estimates – Active Mode 1 MHz, 1.8V: 300 µA 32 kHz, 1.8V: 20 µA (including oscillator) – Power-down Mode < 0.2 µA at 1.8V

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8-bitMicrocontroller with 2K Bytes In-System Programmable Flash ATtiny2313/V Preliminary

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Rev. 2543C–AVR–12/03

1

Pin Configurations

Figure 1. Pinout ATtiny2313

PDIP/SOIC
(RESET/dW)PA2 (RXD)PD0 (TXD)PD1 (XTAL2)PA1 (XTAL1)PA0 (CKOUT/XCK/INT0)PD2 (INT1)PD3 (T0)PD4 (OC0B/T1)PD5 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC PB7(UCSK/SCK/PCINT7) PB6(DO/PCINT6)PB5(DI/SDA/PCINT5) PB4(OC1B/PCINT4) PB3(OC1A/PCINT3) PB2(OC0A/PCINT2) PB1(AIN1/PCINT1) PB0(AIN0/PCINT0) PD6(ICP)

MLF Top View
PD1(TXD) PD0(RXD) PA2(RESET/dW) VCC PB7(UCSK/SCK/PCINT7) PB6(DO/PCINT6) PB5(DI/SDA/PCINT5) NC 32 31 30 29 28 27 26 25

NC (XTAL2)PA1 (XTAL1)PA0 NC NC (CKOUT/XCK/INT0)PD2 NC NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

24 23 22 21 20 19 18 17

NC PB4(OC1B/PCINT4) NC NC NCPB3(OC1A/PCINT3) PB2(OC0A/PCINT2) NC

NOTE: Bottom pad should be Soldered to ground.

2

ATtiny2313/V
2543C–AVR–12/03

(INT1)PD3 (T0)PD4 (OC0B/T1)PD5 GND (ICP)PD6 (AIN0/PCINT0)PB0 (AIN1/PCINT1)PB1 NC

ATtiny2313/V
Overview
The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, theATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Block Diagram
Figure 2. Block Diagram

XTAL1 PA0 - PA2

XTAL2

PORTA DRIVERS

VCC

DATA REGISTER PORTA

DATA DIR. REG. PORTA

INTERNAL CALIBRATED OSCILLATOR

8-BIT DATA BUS GND PROGRAM COUNTER STACK POINTER

INTERNAL OSCILLATOROSCILLATOR

WATCHDOG TIMER MCU CONTROL REGISTER MCU STATUS REGISTER

TIMING AND CONTROL

RESET

PROGRAM FLASH

SRAM

ON-CHIP DEBUGGER

INSTRUCTION REGISTER

GENERAL PURPOSE REGISTER

TIMER/ COUNTERS INTERRUPT UNIT

INSTRUCTION DECODER

EEPROM CONTROL LINES ALU USI STATUS REGISTER

PROGRAMMING LOGIC

SPI

USART

ANALOG COMPARATOR

DATA REGISTER PORTB

DATA DIR. REG.PORTB

DATA REGISTER PORTD

DATA DIR. REG. PORTD

PORTB DRIVERS

PORTD DRIVERS

PB0 - PB7

PD0 - PD6

3
2543C–AVR–12/03

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one...