Controlador Ppi

Week 11 Programmable Interrupt Controller

Expanding the Interrupt Structure

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Operation
• If any of the IR inputs becomes a logic 0, then the output of the NAND gate goes to logic 1 and requests an interrupt through the INTR input • Single interrupt request • What if IR0 and IR1 are active at the same time? INTERRUPT VECTOR • The interrupt vector is generated INPUT is FCh IR0 FEh • Ifthe IR0 input is to have higher IR1 FDh priority, the vector address for IR0 is stored at vector location IR2 FBh FCh IR3 F7h • The entire top half of the vector table and its 128 interrupt vectors IR4 EFh must be used to accommodate all possible conditions IR5 DFh • This seems wasteful but IR6 BFh it may be cost effective in simple systems 3

Daisy Chained Interrupt
The task of locatingwhich interrupt became active is up to the interrupt service procedure
C1 C2 MASK1 MASK2 POLL EQU 504h EQU 604h EQU 1 ; INTRB EQU 8 ;INTRA PROC FAR USES AX DX MOV DX, C1 IN AL, DX TEST AL, MASK1 JNZ LEVEL_0 TEST AL, MASK2 JNZ LEVEL_1 MOV DX, C2 IN AL, DX TEST AL, MASK1 JNZ LEVEL_2 JMP LEVEL_3 ENDP
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POLL

8259 Programmable Interrupt Controller
The 8259 programmable interrupt controller (PIC)adds eight vectored priority encoded interrupts to the microprocessor. This controller can be expanded without additional hardware to accept up to 64 interrupt requests. This requires a master 8259 and eight 8259 slaves.

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82C59A Programmable Interrupt Controller
• Block diagram of 82C59A
– It is treated by the host processor as a peripheral device. – It is configured by the host pocessorto select functions. – Chip Select is again used to address the 82C59A when necessary.
• A0 address selects different command words within the 8259

– INT and INTA¯ ared used as the handshaking interface.
• INT output connects to the INTR pin from the master and is connected to a master IR pin on a slave • In a system with master and slaves, only the master INTA ¯ signal is connected.

–Interrupt inputs IR0 to IR7 can be configured as either level-sensitive or edge-triggered inputs. Edge-triggered inputs become active on 0 to 1 transitions. – Cascade interface CAS0-CAS2 and SP¯/EN¯:
• Cascade interface CAS0-CAS2 carry the address of the slave to be serviced. • SP¯/EN¯ :=1 selects the chip as the master in cascade mode. : in single mode it becomes the enable output for the datatransiever
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82C59A Programmable Interrupt Controller

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82C59A Programmable Interrupt Controller
• Internal architecture of the 82C59A:
– Data bus buffer and read-write logic: are used to configure the internal registers of the chip. – Interrupt mast register (IMR): is used to enable or mask out the individual interrupt inputs through bits M0 to M7. 0= enable, 1= masked out. – Interruptrequest register (IRR): is used to indicate all interrupt levels requesting service. – In service register (ISR): is used to store all interrupt levels which are currently being serviced. – Priority resolver: This block determines the priorities of the bits set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during the INTA¯ sequence. –Cascade-buffer comparator: Sends the address of the selected chip to the slaves in the master mode and decodes the status indicated by the master to find own address to respond.

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Interrupt Sequence
• One or more of the INTERRUPT REQUEST lines (IR0 - IR7) are raised high, setting the corresponding IRR bit(s). • The 82C59A evaluates those requests in the priority resolver and sends an interrupt (INT) tothe CPU, if appropriate. • The CPU acknowledges the lNT and responds with an INTA pulse. • The 82C59A does not drive the data bus during the first INTA pulse. • The 80C86/88/286 CPU will initiate a second INTA pulse. During this INTA pulse, the appropriate ISR bit is set and the corresponding bit in the IRR is reset. The 82C59A outputs the 8-bit pointer onto the data bus to be read by the CPU....