Diseño fisico contador 4 bits

4 January 2010

DesiGN OF dIGITAL INTEGRATED CIRCUITS

Design of Four Bits Counter

Moisés Emmanuel Garcia Romero

Figure 1

Abstract – This paper chiefly shows the design of a four bits counter, also the design of FF D, FF T an improved version of FF T with enable and reset, and simple CMOS AND gated with two inputs.
LIST OF SHORTENINGS USED
AND And gate
CLK Clock of FF
D Input ofFF D
En Enable of FF
FF Flip flop
nXXX Signal XXX negated
Q Output of FF
SEL Saving selector
rst Reset of FF

INTRODUCTION
To build counters FFs are used. In the development of this project I used only FF T with reset and enable and the needed AND gates, but first I designed FF D and T, so I will explain them first.
FLIP FLOP D
To create this FF I thought about a circuit that memorizesits last value in the input. See Figure 1.
In this circuit when SEL=’1’ the value of In is saved at Out, because of the feedback with an inversor at the main inversor. When SEL=’0’, Out keeps the last value of In before SEL became ‘0’, as we can see in Figure 2.
Figure 2

SEL=CLK
IN=D
V(1)=OUT

This is not enough to build a FF because we want to save the value at the input while a risingedge at SEL happens. So I decided to connect two of these circuits as shown in figure 3.

Figure 3

Figure 4

While CLK=’0’ the first circuit saves the value of D and when CLK=’1’ the second circuits saves the value of the output of the first circuit, so this should work like a FF D. Simulations on figure 4.

It doesn’t seem to work. When the circuits are initialized both have ‘1’ at theiroutputs. When the first ‘1’ at D is saved the output of the whole circuit stills at ‘1’. But when the circuit tries to save a ‘0’, it doesn’t work. It is because of the short circuit formed while CLK=’1’ and transistors with * are exited. As the short circuit is read as ‘1’, the ‘1’ of the first circuit can’t be transmitted to the second circuit (Figure 5).
Figure 5
Figure 6

Figure 7

Inthe simulations we only see the short circuit between the first and the second circuit but it will happen too with the circuit that connects to terminal D. To solve this problem I only add a transistor in each circuit to avoid that short circuit. Then when transmission gate * or ** is conducting the transistor * or ** isn’t doing so (Figure 6), simulations on figure 7. Now it works like a FF D.Let’s size the transistors.
I designed the transistors to get tHL=tLH because I think that has the same importance transmit ‘1’ than ‘0’. Since I’m using 0.25µm technology the width of transistor results in wp=1,25µm and wn=1,25µm and wp for transmission gates is 0,625 µm. See figure 8.

Table 1
CLK | Q |
| D |

Figure 8

FLIP FLOP T
The operation of FF T is almost the same that FF D,the difference is that FF T has no input D but its output toggles every rising edge of CLK.
Making the most of the circuit of FF D, I decided to connect input D to node * as shown in figure 9.
Figure 9

This feedback needs to resize transistors to keep tHL=tLH. Only wn increases to 1.625µm. See figure 10.
In figure 11 can be seen the behavioral that I was looking for.

Figure 10

Figure11

FLIP FLOP T WITH RESET AND ENABLE

As I’m supposed to design a counter, it will need a reset to start the count and an enable to make it synchronous.
Reset puts Q to ‘0’, so I put an NMOS in Q activated by rst, other NMOS at the first part of the circuit to reset that par too, and finally a transmission gate activated by rst before the transmission gate activated by CLK.
Table 2
CLK |Q[n-1] | Q[n] |
| 1 | 0 |
| 0 | 1 |

Figure 12

Figure 13

Figure 14

Figure 15

To create the Enable input I put a multiplexer with inputs: Q and nQ. When En=’1’ the multiplexer lets nQ pass through to obtain toggle effect, and when En=’0’ Q pass through the multiplexer and the circuit keeps the same value. Enable also allow or deny the pass of CLK, this to avoid unnecessary...