Electronika

SEVENTH EDITION

ELECTRONIC DEVICES AND CIRCUIT THEORY
ROBERT BOYLESTAD LOUIS NASHELSKY

PRENTICE HALL
Upper Saddle River, New Jersey Columbus, Ohio

Contents

PREFACE ACKNOWLEDGMENTS

xiii xvii

1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17

SEMICONDUCTOR DIODES
Introduction 1 Ideal Diode 1 Semiconductor Materials 3 Energy Levels 6 ExtrinsicMaterials—n- and p-Type 7 Semiconductor Diode 10 Resistance Levels 17 Diode Equivalent Circuits 24 Diode Specification Sheets 27 Transition and Diffusion Capacitance 31 Reverse Recovery Time 32 Semiconductor Diode Notation 32 Diode Testing 33 Zener Diodes 35 Light-Emitting Diodes (LEDs) 38 Diode Arrays—Integrated Circuits 42 PSpice Windows 43

1

2
2.1 2.2 2.3

DIODE APPLICATIONS
Introduction51 Load-Line Analysis 52 Diode Approximations 57

51

v

2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13

Series Diode Configurations with DC Inputs 59 Parallel and Series-Parallel Configurations 64 AND/OR Gates 67 Sinusoidal Inputs; Half-Wave Rectification 69 Full-Wave Rectification 72 Clippers 76 Clampers 83 Zener Diodes 87 Voltage-Multiplier Circuits 94 PSpice Windows 97

3
3.1 3.2 3.33.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12

BIPOLAR JUNCTION TRANSISTORS
Introduction 112 Transistor Construction 113 Transistor Operation 113 Common-Base Configuration 115 Transistor Amplifying Action 119 Common-Emitter Configuration 120 Common-Collector Configuration 127 Limits of Operation 128 Transistor Specification Sheet 130 Transistor Testing 134 Transistor Casing and TerminalIdentification 136 PSpice Windows 138

112

4
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13

DC BIASING—BJTS
Introduction 143 Operating Point 144 Fixed-Bias Circuit 146 Emitter-Stabilized Bias Circuit 153 Voltage-Divider Bias 157 DC Bias with Voltage Feedback 165 Miscellaneous Bias Configurations 168 Design Operations 174 Transistor Switching Networks 180 Troubleshooting Techniques 185 PNPTransistors 188 Bias Stabilization 190 PSpice Windows 199

143

5
5.1 5.2 5.3 vi
Contents

FIELD-EFFECT TRANSISTORS
Introduction 211 Construction and Characteristics of JFETs 212 Transfer Characteristics 219

211

5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13

Specification Sheets (JFETs) 223 Instrumentation 226 Important Relationships 227 Depletion-Type MOSFET 228 Enhancement-TypeMOSFET 234 MOSFET Handling 242 VMOS 243 CMOS 244 Summary Table 246 PSpice Windows 247

6
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13

FET BIASING
Introduction 253 Fixed-Bias Configuration 254 Self-Bias Configuration 258 Voltage-Divider Biasing 264 Depletion-Type MOSFETs 270 Enhancement-Type MOSFETs 274 Summary Table 280 Combination Networks 282 Design 285 Troubleshooting 287P-Channel FETs 288 Universal JFET Bias Curve 291 PSpice Windows 294

253

7
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8

BJT TRANSISTOR MODELING
Introduction 305 Amplification in the AC Domain 305 BJT Transistor Modeling 306 The Important Parameters: Zi, Zo, Av, Ai 308 The re Transistor Model 314 The Hybrid Equivalent Model 321 Graphical Determination of the h-parameters 327 Variations of TransistorParameters 331

305

8
8.1 8.3 8.3 8.4 8.3 8.6

BJT SMALL-SIGNAL ANALYSIS
Introduction 338 Common-Emitter Fixed-Bias Configuration 338 Voltage-Divider Bias 342 CE Emitter-Bias Configuration 345 Emitter-Follower Configuration 352 Common-Base Configuration 358

338

Contents

vii

8.7 8.8 8.9 8.10 8.11 8.12 8.13

Collector Feedback Configuration 360 Collector DC Feedback Configuration 366Approximate Hybrid Equivalent Circuit 369 Complete Hybrid Equivalent Model 375 Summary Table 382 Troubleshooting 382 PSpice Windows 385

9
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 9.15

FET SMALL-SIGNAL ANALYSIS
Introduction 401 FET Small-Signal Model 402 JFET Fixed-Bias Configuration 410 JFET Self-Bias Configuration 412 JFET Voltage-Divider Configuration 418 JFET...