Electrónica

hora_unidades, min_unidades, seg_unidades : out INTEGER RANGE 0 TO 9;
min_decenas, seg_decenas : out INTEGER RANGE 0 TO 5;
pm : out bit);
end General;

architectureBehavioral of General is

signal alambre1, alambre2, alambre3: bit;
signal habilitado : bit;

component Mod60 is
Port ( CLK, enable : in BIT;
decenas : out INTEGER RANGE0 TO 5;
unidades : out INTEGER RANGE 0 TO 9;
conteo_terminal : out BIT);
end component Mod60;

component Mod12 is
Port ( CLK, enable : in bit;inferior : out INTEGER RANGE 0 TO 9;
superior : out INTEGER RANGE 0 TO 1;
pm : out BIT);
end component Mod12;

component Comparador is
Port ( Cont2 : inSTD_LOGIC_VECTOR (3 downto 0);
Cont3 : in STD_LOGIC_VECTOR (3 downto 0);
Cont4 : in STD_LOGIC_VECTOR (3 downto 0);
Cont5 : in STD_LOGIC_VECTOR (3 downto 0);alarm2 : out STD_LOGIC_VECTOR (3 downto 0);
alarm3 : out STD_LOGIC_VECTOR (3 downto 0);
alarm4 : out STD_LOGIC_VECTOR (3 downto 0);
alarm5 : out STD_LOGIC_VECTOR (3downto 0));
end component Comparador;

begin

habilitado <= '1';

Segundos: Mod60
port map (clk => pps_60,
enable => habilitado,
conteo_terminal => alambre1);Segundos2: Mod60
port map (clk => pps_60,
enable => alambre1,
unidades => seg_unidades,
decenas => seg_decenas,
conteo_terminal =>alambre2);

Minutos: Mod60
port map (clk => pps_60,
enable => alambre2,
unidades => min_unidades,
decenas => min_decenas,
conteo_terminal=> alambre3);

Hora: Mod12
port map (clk => pps_60,
enable => alambre3,
inferior => hora_unidades,
superior => hora_decenas,
pm =>...