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|August 1986 |
|Revised March 2000 |
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|DM74LS194A |
|4-Bit Bidirectional Universal Shift Register|
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|General Description Features |
|This bidirectional shift register is designed to incorporate ■ Parallel inputs and outputs virtually all ofthe |
|features a system designer may want in a ■ Four operating modes: |
|shift register; they feature parallel inputs, parallel outputs, Synchronous parallel load |
|right-shift and left-shift serial inputs, operating-mode-con- |
|trol inputs, and a directoverriding clear line. The register Right shift has four distinct modes of operation, |
|namely: Left shift |
|Parallel (broadside) load Do nothing |
|Shift right (in the direction QA toward QD) ■ Positiveedge-triggered clocking |
|Shift left (in the direction QD toward QA) ■ Direct overriding clear |
|Inhibit clock (do nothing) |
|Synchronous parallel loading is accomplished by applying the four bits of data and taking both modecontrol inputs, |
|S0 and S1, HIGH. The data is loaded into the associated flip-flops and appear at the outputs after the positive |
|transi- tion of the clock input. During loading, serial data flow is inhibited. |
|Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is HIGH and S1 is LOW. |
|Serial data forthis mode is entered at the shift-right data input. When S0 is LOW and S1 is HIGH, data shifts left |
|synchronously and new data is entered at the shift-left serial input. |
|Clocking of the flip-flop is inhibited when both mode control inputs are LOW. |
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|Ordering Code: |
|Order Number |Package Number |Package Description |
|DM74LS194AM |M16A |16-Lead Small Outline Integrated Circuit (SOIC), JEDECMS-012, 0.150 Narrow |
|DM74LS194AN |N16E |16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
|Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. |
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