High Performance Ftl Ripple Carry Adders In Cmos Technologies: Experimental Results

Abstract— This work presents the experimental results, from chip measurements, of ripple carry adder cells using a new CMOS logic family, based on the feedthrough evaluation concept. The feedthrough logic (FTL) allows for a partial evaluation in a computational block before its input signals are valid, an do the quick final evaluation as soon as the inputs arrive. The FTL is well suited toarithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, from the chip measurements, show that our 14–bit low power FTL adder performs faster, (2.6 times smaller propagation time delay, and 1.85 timeshigher maximum frequency), and provides a better energy efficiency (67.9% saving), when compared with the dynamic domino CMOS logic style. The 18–bit high speed FTL, working at its maximum frequency, outperforms the dynamic domino logic in terms of the propagation delay (19.5 times less), maximum frequency (12.1 times more), and energy efficiency per bit (96.7% saving). Index Terms— Feedthrough logic,CMOS digital integrated circuits, CMOS logic circuits, digital arithmetic, high speed integrated circuits, low power design.

I. INTRODUCTION
Reduction in the energy dissipation, in CMOS integrated circuits, while maintaining the high performance, has been the topic of intense research in the recent past. The proposed design techniques trade power for performance in the delay criticalsections of the circuit [1]–[5]. To achieve this goal the mix of dynamic and static circuit styles [2], use of dual supply voltages [3]–[5], and dual V T transistors [5], have been proposed. To improve the performance of arithmetic circuits, with a very long logic depth, a new logic family called feedthrough logic (FTL) was proposed by the authors for the integrated circuits in GaAs technology [6], [7].The FTL principle of operation was presented in [8]. Unlike other dynamic logic families, FTL resets the output nodes to low when the clock signal (φ) is set high. When the clock signal goes low, cascaded gates rise to their switching threshold value of VTH . During this low phase of φ, cascaded stages evaluate their inputs in a domino–like fashion, with the output nodes only making a partialtransition from the VTH point to high or low logic levels. This fact results in very fast evaluation time in the computational blocks. Furthermore, the well known problems associated with the domino logic — such as the limitation of non–inverting only logic, charge redistribution and the need for output inverters — are completely eliminated [9], thus reducing the chip area and delay, and improving theperformance. The FTL concept was successfully introduced by the authors in CMOS technologies for high performance and low power arithmetic circuits [10]. We also extended our research to high speed circuits, and analyzed the adder sensitivity against the capacitive load, temperature, power supply, process variation and noise coupling for the high speed and low power FTL logic families [11]. Ourresults in [11] showed substantial performance improvement of FTL with respect to standard static fully complementary CMOS and pseudo–NMOS logic design styles. In this work, we present the chip measurement results of the FTL Ripple Carry Adder (RCA) cells, using the 0.13 µm 1.2 V / 3.3 V 1P8M Logic High Speed Process from UMC. Obtained results demonstrate that FTL adders outperforms the dynamicdomino RCA in terms of propagation delay, maximum frequency and energy efficiency.

A. Organization of the Paper
Section II sums up the basic concepts related to the design of high performance RCA cells in the FTL logic family. Next, in Section III, we expose the measurement procedure and the obtained performance results for a set of manufatured FTL adders. We compare the results of the FTL...