Ingenierìa En Sistemas

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541
Data sheet acquired from Harris Semiconductor SCHS189C

January 1998 - Revised July 2004

High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State
Description
The ’HC540 and CD74HCT540 are Inverting Octal Buffers and Line Drivers with Three-State Outputs and the capability to drive 15 LSTTL loads. The ’HC541 and ’HCT541 areNonInverting Octal Buffers and Line Drivers with Three-State Outputs that can drive 15 LSTTL loads. The Output Enables (OE1) and (OE2) control the Three-State Outputs. If either OE1 or OE2 is HIGH the outputs will be in the high impedance state. For data output OE1 and OE2 both must be LOW.

Features
• ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting

[ /Title (CD74 HC540 , CD74HCT54 0, CD74 HC541 , CD74 HCT54

• ’HC541, ’HCT541 . . . . . . . . . . . . . . . . . . . . . . Non-Inverting • Buffered Inputs • Three-State Outputs • Bus Line Driving Capability • Typical Propagation Delay = 9ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS InputCompatibility, Il ≤ 1µA at VOL, VOH

Ordering Information
PART NUMBER CD54HC540F3A CD54HC541F3A CD54HCT541F3A CD74HC540E CD74HC540M CD74HC540M96 CD74HC541E CD74HC541M CD74HC541M96 CD74HC541PW CD74HC541PWR CD74HCT540E CD74HCT540M CD74HCT540M96 CD74HCT541E CD74HCT541M CD74HCT541M96 TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 20 Ld CERDIP 20 Ld CERDIP 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC 20 Ld TSSOP 20 Ld TSSOP 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel.

CAUTION: These devicesare sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

© 2004, Texas Instruments Incorporated

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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Pinouts
CD54HC540 (CERDIP) CD74HC540, CD74HCT540 (PDIP, SOIC) TOP VIEW
OE A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 20 VCC 19 OE2 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 11 Y7CD54HC541, CD54HCT541 (CERDIP) CD74HC541 (PDIP, SOIC, TSSOP) CD74HCT541 (PDIP, SOIC) TOP VIEW
OE1 A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 20 VCC 19 OE2 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 11 Y7

GND 10

GND 10

Functional Diagram
OEA OEB 540 D0 Y0 541 Y0

D1

Y1

Y1

D2

Y2

Y2

D3

Y3

Y3

D4

Y4

Y4

D5

Y5

Y5

D6

Y6

Y6

D7

Y7

Y7

2CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

TRUTH TABLE INPUTS OE1 L H X L OE2 L X H L An H X X L 540 L Z Z H OUTPUTS 541 H Z Z L

H = HIGH Voltage Level L = LOW Voltage Level X= Don’t Care Z = High Impedance

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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DCInput Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V...