Shift Register Hoja De Datos

INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
Product specification
Supersedes data ofSeptember 1993
File under Integrated Circuits, IC06

1998 Jun 04

Philips Semiconductors

Product specification

8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state

74HC/HCT595

FEATURES

DESCRIPTION

• 8-bit serial input

The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They arespecified in compliance with JEDEC
standard no. 7A.

• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear

The “595” is an 8-stage serial shift register with a storage
register and 3-state outputs. The shift register and storage
register have separate clocks.

• 100 MHz (typ) shift out frequency
• Output capability:
– paralleloutputs; bus driver

Data is shifted on the positive-going transitions of the
SHCP input. The data in each register is transferred to the
storage register on a positive-going transition of the STCP
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.

– serial output; standard
• ICC category: MSI.
APPLICATIONS
•Serial-to-parallel data conversion

The shift register has a serial input (DS) and a serial
standard output (Q7’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.

• Remote controlholding register.

QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
TYP.
SYMBOL PARAMETER

CONDITIONS

UNIT
HC

tPHL/tPLH

16

propagation delay

HCT
21

CL = 15 pF; VCC = 5 V

SHCP to Q7’

ns

STCP to Qn

17

20

ns

MR to Q7’

14

19

ns

fmax

maximum clock frequency SHCP, STCP

100

57

MHz

CI

input capacitance

3.53.5

pF

CPD

power dissipation capacitance per package

115

130

pF

notes 1 and 2

Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC thecondition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V.

1998 Jun 04

2

Philips Semiconductors

Product specification

8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state

74HC/HCT595

ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME

DESCRIPTION

VERSION

74HC595N

DIP16

plastic dual in-line package; 16 leads (300mil); long body

SOT38-1

74HC595D

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

74HC595DB

SSOP16

plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

74HC595PW

TSSOP16

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

74HCT595N

DIP16

plastic dual in-line package; 16 leads(300 mil); long body

SOT38-1

74HCT595D

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

PINNING
SYMBOL

PIN

Q0 to Q7

DESCRIPTION

15, 1 to 7

GND

8

parallel data output
ground (0 V)

Q7’

9

serial data output

MR

10

master reset (active LOW)

SHCP

11

shift register clock input

STCP

12

storage register...