Dm74ls194a 4-bit bidirectional universal shift register

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DM74LS194A 4-Bit Bidirectional Universal Shift Register

August 1986 Revised March 2000

DM74LS194A 4-Bit Bidirectional Universal Shift Register
General Description
This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register; they feature parallel inputs, parallel outputs, right-shift and left-shift serial inputs,operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, HIGH.The data is loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is HIGH and S1 is LOW. Serial data for this mode is entered at the shift-right data input. When S0 is LOW and S1 is HIGH, data shiftsleft synchronously and new data is entered at the shift-left serial input. Clocking of the flip-flop is inhibited when both mode control inputs are LOW.

s Parallel inputs and outputs s Four operating modes: Synchronous parallel load Right shift Left shift Do nothing s Positive edge-triggered clocking s Direct overriding clear

Ordering Code:
Order Number DM74LS194AM DM74LS194ANPackage Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

© 2000 Fairchild Semiconductor Corporation

DS006407 DM74LS194A

Function Table
Inputs Clear L H H H H H H H Mode S1 X X H L L H H L S0 X X H H H L L L Clock X L ↑ ↑ ↑ ↑ ↑ X Serial Left X X X X X H L X Right X X X H L X X X A X X a X X X X X Parallel B X X b X X X X X C X X c X X X X X D X X d X X X X X QA L QA0 a H L QBn QBn QA0 Outputs QB L QB0 b QAn QAn QCn QCn QB0 QC L QC0 c QBn QBn QDn QDn QC0 QD L QD0 d QCn QCn H L QD0

H = HIGH Level(steady state) L = LOW Level (steady state) X = Don’t Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level a, b, c, d = The level of steady state input at inputs A, B, C or D, respectively. QA0, QB0, QC0, Q D0 = The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established. QAn, QBn, QCn, Q Dn = The level of QA, QB, QC,respectively, before the most-recent ↑ transition of the clock.

Logic Diagram



Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 0°C to +70°C −65°C to +150°C 7V 7V
Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot beguaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tW tSU tH tREL TA Supply Voltage HIGH Level InputVoltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 4) Setup Time (Note 4) Hold Time (Note 4) Clear Release Time (Note 4) Free Air Operating Temperature Clock Clear Mode Data 0 0 20 20 30 20 0 25 0 70 Parameter Min 4.75 2 0.8 −0.4 8 25 20 Nom 5 Max 5.25 Units V V V mA mA MHz ns ns ns ns °C

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