Introduccion Al Propeller

Our periodic column for PIC programming enlightenment

PIC n’ Mix
What is it?

Mike Hibbett

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Introducing The Propeller Processor
is a nice piece of engineering, with some interesting features, but as Robert pointed out, the number of free I/O pins is limited. So, what exactly is the Propeller Chip? Conceived in the late 1990s by engineers at Parallax Inc, it came to the market in2006. Frustrated by what they saw as inadequacies in existing microcontroller products, it was originally intended to be a small single-core processor, but through an iterative process of design, test, write software and evaluate, and with falling silicon costs, they ended up at an eight-core controller on a single die. While we may be becoming used to multiple processing cores on our PCs, courtesyor Intel and AMD, multicore processors are very unusual in the small microcontroller market (in fact we have not seen another – let us know if you have!) This processor is also readily available to the hobbyist, at a very reasonable cost – 5US$ from Digikey, £9 from Farnell. Supplied in both a standard 40-pin DIL and a QFP surface mount format. Having eight ‘cores’ on the chip does not mean thatyou have eight completely

n February’s issue, Robert Penfold gave an interesting introduction to the Propeller processor demo board from Parallax, and starting this month we thought we would take an in-depth look at the processor, and build a development circuit of our own. We’ve been searching for a number of months for a solution to the problem of generating colour video on a small processor,and it was quite by coincidence that Robert’s article should appear just days after we discovered the Propeller chip and its on-chip hardware support for generating colour video. The demo board

Multiple cores

Fig.1. Propeller architecture

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independent processors sitting inside a single package.There are eight 32-bit processing units with their own independent program and data area, but sharing access to common peripherals. The setup is shown in Fig.1. Within each processor is 2KB of RAM that serves as both program and data storage. Each processor also has two counters, video generation hardware and an I/O peripheral to drive the single 32-bit-wide I/O port. As you can see, everyprocessor can drive all 32 I/O pins. It’s a flexible arrangement designed so that the individual processors, called ‘Cogs’, can drive individual pins, or even share control of a single pin if desired. Interestingly, there are no interrupt capabilities on this device, to which some will give a sigh of relief. The intention is that tasks which would normally require an interrupt, such as an RS232interface, will be handled by a dedicated Cog. This would poll the receive pin and bit-bash the transmit pin, and write received data into a buffer in common memory, to be picked up and processed by another Cog. Although 2KB of data and program space sounds small, this is an allocation per Cog – so there is a total of 16KB for the chip as a whole. In addition, there is a single block of 32KB RAM that isaccessible by all Cogs. Access to this memory is coordinated through the ‘Hub’, a synchronisation mechanism that ensures only one Cog can be reading or writing to it at any one time. While all Cogs run in parallel (at up to 20 million instructions per second each, for a maximum performance of 160MIPS!) access to the shared memory has to wait until the Hub allocates a processor a time slot. The Hub‘spins round’ at a rate of half the system clock speed, and so a Cog can gain access to the shared memory once every 16 clock cycles. Every Cog is allocated a slot (even if that Cog is not use ) and so the timing of access to shared memory is deterministic, allowing the software developer to optimise their software to account for the delay when waiting for the next time slot. The Hub arrangement...