Adc Convertidor

®

ADC0803, ADC0804
Data Sheet August 2002 FN3094.4

8-Bit, Microprocessor-Compatible, A/D Converters
The ADC080X family are CMOS 8-Bit, successiveapproximation A/D converters which use a modified potentiometric ladder and are designed to operate with the 8080A control bus via three-state outputs. These converters appear to the processor as memory locations or I/O ports, and hence nointerfacing logic is required. The differential analog voltage input has good commonmode-rejection and permits offsetting the analog zero-inputvoltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.

Features
• 80C48 and 80C80/85 Bus Compatible - No Interfacing Logic Required • Conversion Time . . . .. . . . . . . . . . . . . . . . . . . . . . 1kΩ). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size, the effects of the voltage drop across this input resistance, due to the average value of the input current, can be compensated by a full scale adjustment while the given source resistor and input bypass capacitor areboth in place. This is possible because the average value of the input current is a precise linear function of the differential input voltage at a constant conversion rate.

Analog Differential Voltage Inputs and CommonMode Rejection
This A/D gains considerable applications flexibility from the analog differential voltage input. The VlN(-) input (pin 7) can be used to automatically subtract afixed voltage value from the input reading (tare correction). This is also useful in 4mA - 20mA current loop conversion. In addition, common-mode noise can be reduced by use of the differential input. The time interval between sampling VIN(+) and VlN(-) is 41/2 clock periods. The maximum error voltage due to this slight time difference between the input voltage samples is given by:
4.5 ∆V E ( MAX ) =( V PEAK ) ( 2πf CM ) -----------f CLK

Input Source Resistance
Large values of source resistance where an input bypass capacitor is not used will not cause errors since the input currents settle out prior to the comparison time. If a lowpass filter is required in the system, use a low-value series resistor (≤1kΩ) for a passive RC section or add an op amp RC active low-pass filter. Forlow-source-resistance applications (≤1kΩ), a 0.1µF bypass capacitor at the inputs will minimize EMI due to the series lead inductance of a long wire. A 100Ω series resistor can be used to isolate this capacitor (both the R and C are placed outside the feedback loop) from the output of an op amp, if used.

where:

∆VE is the error voltage due to sampling delay, VPEAK is the peak value of thecommon-mode voltage, fCM is the common-mode frequency. For example, with a 60Hz common-mode frequency, fCM , and a 640kHz A/D clock, fCLK , keeping this error to 1/4 LSB (~5mV) would allow a common-mode voltage, VPEAK , given by:
∆V E ( MAX ) ( f V PEAK = ------------------------------------------------- , ( 2πf CM ) ( 4.5 )
CLK )

Stray Pickup
The leads to the analog inputs (pins 6 and 7) should bekept as short as possible to minimize stray signal pickup (EMI). Both EMI and undesired digital-clock coupling to these inputs can cause system errors. The source resistance for these inputs should, in general, be kept below 5kΩ. Larger values of source resistance can cause undesired signal pickup. Input bypass capacitors, placed from the analog inputs to ground, will eliminate this pickup but cancreate analog scale errors as these capacitors will average the transient input switching currents of the A/D (see Analog Input Current). This scale error depends on both a large source resistance and the use of an input bypass capacitor. This error can be compensated by a full scale adjustment of the A/D (see Full Scale Adjustment) with the source resistance and input bypass capacitor in place,...