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Transistor Level Synthesis for Static CMOS Combinational Circuits 
Chia-Pin R. Liu Jacob A. Abraham Computer Engineering Research Center The University of Texas at Austin Austin, TX 78712 fcpliu,jaag@cerc.utexas.edu Abstract
This paper introduces a novel framework to synthesize static CMOS circuits at the transistor level. A new class of binary decision diagrams (BDDs) which representinverting Boolean functions, called Transistor Mapped BDDs (TMBDDs), is used in the synthesis process. There is a one-toone correspondence between a transistor netlist and its TMBDD. Nodes in a TM-BDD represent gate inputs and the edges represent the transistors in the netlist. TM-BDDs can be optimized using BDD operations, and the data structure can retain device aspect ratios and geometries forperformance optimization. The synthesis process involves a transformation from logic functions to transistor netlists using TM-BDDs. We show how a transistor netlist can be automatically generated during a depth-first traversal on a TMBDD. The synthesis process is not only independent of any library, but also capable of generating a cell library for a particular circuit. Experimental results demonstratingthe reduction of transistor counts are presented.

1 Introduction
CMOS technology has firmly established a dominant role in today’s electronics industry. Automated tools help designers to manipulate more transistors on a chip and shorten the design cycle. In particular, logic synthesis tools have contributed significantly to reducing cycle times. Synthesis can be seen as a set of transformationsand optimizations from high-level specifications to low-level implementations. Each transformation between two levels involves restructuring of technology dependent information. All VLSI designs are ultimately implemented at the transistor level. Technology mapping is a task of transforming an optimized logic network into an interconnection of
 This research was supported by the Texas TechnologyDevelopment and Transfer Program under Project 003658-433 at the University of Texas at Austin.

functional blocks consisting of transistor netlists. In fullcustom designs, manual generation of transistor netlists for each functional block is done, but this is an extremely timeconsuming and difficult task. In the standard-cell methodology, cell library binding utilizes a specific pre-characterizedcell library which may take advantage of optimized cell layout and accurate characterization of each cell. However, with rapid advances in process technologies and circuit modeling techniques, cell libraries may not meet performance goals when migrated to new process technologies. Generating and maintaining a cell library is also a timeconsuming process [1]. It is critical, therefore, to createnew libraries in a timely fashion and to provide methodologies for evaluating as well as re-targeting designs to new process technologies. Ideally, technology mapping should not be limited by any particular cell library. Cell libraries should have some degree of flexibility to meet requirements or features of an individual design. Furthermore, cell libraries should be generated based on differentclasses of designs. Since transistor-level descriptions of a design, such as SPICE netlists, are a refinement of the logic design, synthesis techniques at this level will allow much better optimizations for area, performance and power than techniques at the logic level. Problem Definition : Given a multi-level logic network at the gate level, transistor-level synthesis is the process for automaticgeneration of transistor netlists, without any predefined cell library. The device aspect ratio (W/L) of each transistor and the device geometry should be preserved for performance analysis, and transistor-level functional cells used in the circuit should be identified for possible further optimization. Wu [6] and Zhu [8] propose methods optimizing switching networks by utilizing shared transistors...