Circuito Integrado

INTEGRATED CIRCUITS

DATA SHEET

74HC4066; 74HCT4066 Quad bilateral switches
Product specification Supersedes data of 2003 Jun 17 2004 Nov 11

Philips Semiconductors

Product specification

Quad bilateral switches

74HC4066; 74HCT4066

FEATURES • Very low ON-resistance: – 50 Ω (typical) at VCC = 4.5 V – 45 Ω (typical) at VCC = 6.0 V – 35 Ω (typical) at VCC = 9.0 V. • Complies withJEDEC standard no. 7A • ESD protection: HBM EIA/JESD22-A114-B exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 °C to +85 °C and −40 °C to +125 °C.

GENERAL DESCRIPTION The 74HC4066 and 74HCT4066 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4066B. They are specified in compliance with JEDEC standard no. 7A. The 74HC4066 and 74HCT4066 have fourindependent analog switches. Each switch has two input/output pins (pins nY or nZ) and an active HIGH enable input pin (pin nE). When pin nE = LOW the belonging analog switch is turned off. The 74HC4066 and 74HCT4066 are pin compatible with the 74HC4016 and 74HCT4016 but exhibit a much lower on-resistance. In addition, the on-resistance is relatively constant over the full input signal range.QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. TYPICAL SYMBOL tPZH/tPZL tPHZ/tPLZ CI CPD CS Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ[(CL + CS) × VCC2 × fo] where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; CS = maximum switch capacitance in pF; VCC = supply voltage in V;N = number of inputs switching; Σ[(CL + CS) × VCC2 × fo] = sum of the outputs. 2. For 74HC4066 the condition is VI = GND to VCC. For 74HCT4066 the condition is VI = GND to VCC − 1.5 V. PARAMETER turn-on time nE to Vos turn-off time nE to Vos input capacitance power dissipation capacitance per switch maximum switch capacitance notes 1 and 2 CONDITIONS 74HC4066 CL = 15 pF; RL = 1 kΩ; VCC = 5 V CL= 15 pF; RL = 1 kΩ; VCC = 5 V 11 13 3.5 11 8 74HCT4066 12 16 3.5 12 8 ns ns pF pF pF UNIT

2004 Nov 11

2

Philips Semiconductors

Product specification

Quad bilateral switches

74HC4066; 74HCT4066

FUNCTION TABLE See note 1. INPUT nE L H Note 1. H = HIGH voltage level. L = LOW voltage level. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74HC4066N 74HCT4066N 74HC4066D74HCT4066D 74HC4066DB 74HCT4066DB 74HC4066PW 74HCT4066PW 74HC4066BQ 74HCT4066BQ PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL 1Y 1Z 2Z 2Y 2E 3E GND 3Y 3Z 4Z 4Y 4E 1E VCC DESCRIPTION independent input/output independent input/output independent input/output independent input/output enable input (active HIGH) enable input (active HIGH) ground (0 V) independent input/output independentinput/output independent input/output independent input/output enable input (active HIGH) enable input (active HIGH) supply voltage Fig.1 Pin configuration DIP14, SO14 and (T)SSOP14.
2Y 2E 3E GND 4 5 6 7
MGR253

SWITCH off on

PINS 14 14 14 14 14 14 14 14 14 14

PACKAGE DIP14 DIP14 SO14 SO14 SSOP14 SSOP14 TSSOP14 TSSOP14 DHVQFN14 DHVQFN14

MATERIAL plastic plastic plastic plastic plasticplastic plastic plastic plastic plastic

CODE SOT27-1 SOT27-1 SOT108-1 SOT108-1 SOT337-1 SOT337-1 SOT402-1 SOT402-1 SOT762-1 SOT762-1

−40 °C to 125 °C −40 °C to 125 °C −40 °C to 125 °C −40 °C to 125 °C −40 °C to 125 °C −40 °C to 125 °C −40 °C to 125 °C −40 °C to 125 °C −40 °C to 125 °C −40 °C to 125 °C

handbook, halfpage

1Y 1Z 2Z

1 2 3

14 VCC 13 1E 12 4E

4066

11 4Y 10 4Z 9 3Z8 3Y

2004 Nov 11

3

Philips Semiconductors

Product specification

Quad bilateral switches

74HC4066; 74HCT4066

terminal 1 index area 1Z 2Z 2Y 2E 3E 2 3 4 5 6

14 VCC

1Y

1

handbook, halfpage

13 1E 12 4E

1Y 13 1E 1Z 2Y 2Z 3Y 3Z 4Y 4Z
MGR254

1 2 4 3 8 9 11 10

4066
VCC(1) 7 8

11 4Y 10 4Z 9 3Z

5

2E

6

3E

GND

3Y

001aac116

12

4E...