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SN74LS175 Quad D Flip-Flop
The LSTTL / MSI SN74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of theClock or D inputs, when LOW. The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.

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• • • • • •

LOW POWER SCHOTTKY

Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Clock to Output Delays of 30 ns Asynchronous Common Reset True and Complement Output InputClamp Diodes Limit High Speed Termination Effects
16 1

GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 – 0.4 8.0 Unit V °C mA mA

PLASTIC N SUFFIX CASE 648

16 1

SOIC D SUFFIX CASE 751B

ORDERING INFORMATION
Device SN74LS175N SN74LS175D Package 16Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel

© Semiconductor Components Industries, LLC, 1999

1

December, 1999 – Rev. 6

Publication Order Number: SN74LS175/D

SN74LS175
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 Q3 15 Q3 14 D3 13 D2 12 Q2 11 Q2 10 CP 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 MR 2 Q0 3 Q0 4 D0 5 D16 Q1 7 Q1 8 GND

LOADING (Note a) PIN NAMES D0 – D3 CP MR Q0 – Q3 Q0 – Q3 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input True Outputs Complemented Outputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. 5 U.L.

NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOGIC SYMBOL
4 5 12 13

9

CP

D0

D1D2

D3

1

MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3

3

2

6

7

11

10 14 15

VCC = PIN 16 GND = PIN 8

LOGIC DIAGRAM
MR CP D3
1 9 13

D2
12

D1
5

D0
4

D Q CP Q CD
14 15

D Q CP Q CD
11 10

D Q CP Q CD
6 7

D Q CP Q CD
3 2

Q3 Q3

Q2 Q2
VCC = PIN 16 GND = PIN 8 = PIN NUMBERS

Q1 Q1

Q0 Q0

http://onsemi.com
2

SN74LS175
FUNCTIONAL DESCRIPTIONThe LS175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW to HIGH Clock (CP) transition, causing individual Q and Q outputs to

follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent ofClock or Data inputs. The LS175 is useful for general logic applications where a common Master Reset and Clock are acceptable.

TRUTH TABLE
Inputs (t = n, MR = H) D L H Outputs (t = n+1) Note 1 Q L H Q H L

Note 1: t = n + 1 indicates conditions after next clock.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter InputHIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 – 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 IIH IIL IOS ICC Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 20 – 0.4 – 100 18 0.5 20 V µA mA mA mA mA IOL = 8.0 mA 0.4 Min 2.0 0.8 – 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All InputsGuaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

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