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DM7490A Decade and Binary Counters

August 1986 Revised March 2000

DM7490A Decade and Binary Counters
General Description
The DM7490A monolithic counter contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five. The counter has a gated zero reset and also has gatedsetto-nine inputs for use in BCD nine’s complement applications. To use the maximum count length (decade or four-bit binary), the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate Function Table. A symmetrical divide-by-ten count can be obtained from the counters by connecting the QD output to the A input and applyingthe input count to the B input which gives a divideby-ten square wave at output QA.

Features
s Typical power dissipation 145 mW s Count frequency 42 MHz

Ordering Code:
Order Number DM7490AN Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram

© 2000 Fairchild Semiconductor Corporation

DS006533www.fairchildsemi.com

DM7490A

Function Tables
BCD Count Sequence (Note 1) Count QD 0 1 2 3 4 5 6 7 8 9 L L L L L L L L H H L L L L H H H H L L Outputs QC QB L L H H L L H H L L QA L H L H L H L H L H

Logic Diagram

BCD Bi-Quinary (5-2) (Note 2) Count QA 0 1 2 3 4 5 6 7 8 9 L L L L L H H H H H L L L L H L L L L H Outputs QD QC L L H H L L L H H L QB L H L H L L H L H L

Reset/Count FunctionTable Reset Inputs R0(1) H H X X L L X
H = HIGH Level L = LOW Level X = Don’t Care Note 1: Output QA is connected to input B for BCD count. Note 2: Output QD is connected to input A for bi-quinary count

Outputs R9(2) X L H L X L X QD L L H QC L L L QB L L L QA L L H

R0(2) H H X L X X L

R9(1) L X H X L X L

The J and K inputs shown without connection are for reference only and arefunctionally at a HIGH level.

COUNT COUNT COUNT COUNT

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2

DM7490A

Absolute Maximum Ratings(Note 3)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0°C to +70°C −65°C to +150°C
Note 3: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH LevelOutput Current LOW Level Output Current Clock Frequency (Note 4) Pulse Width (Note 4) tREL TA Reset Release Time (Note 4) Free Air Operating Temperature A B A B Reset 0 0 15 30 15 25 0 70 ns °C ns Parameter Min 4.75 2 0.8 −0.8 16 32 16 Nom 5 Max 5.25 Units V V V mA mA MHz

Note 4: TA = 25°C and VCC = 5V.

DC Electrical Characteristics
over recommended operating free air temperature range(unless otherwise noted) Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage HIGH Level Input Current IIL LOW Level Input Current IOS ICC Short Circuit Output Current Supply Current Conditions VCC = Min, II = −12 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max (Note 6) VCC = Max VI = 2.7V VCC = Max VI = 0.4V VCC= Max (Note 7) VCC = Max (Note 8) A Reset B A Reset B −18 29 2.4 3.4 0.2 0.4 1 80 40 120 −3.2 −1.6 −4.8 −57 42 mA mA mA µA Min Typ (Note 5) Max −1.5 Units V V V mA

Input Current @ Max Input Voltage VCC = Max, VI = 5.5V

Note 5: All typicals are at VCC = 5V, TA = 25°C. Note 6: QA outputs are tested at IOL = Max plus the limit value of IIL for the B input. This permits driving the B input...
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