Haces

MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS P–Channel and N–Channel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
provide logic level conversion using only one supplyvoltage, VDD.
The input–signal high level (VIH) can exceed the VDD supply
voltage for logic level conversions. Two TTL/DTL loads can be driven
when the devices are used as a CMOS–to–TTL/DTL converter (VDD
= 5.0 V, VOL v 0.4 V, IOL ≥ 3.2 mA).
Note that pins 13 and 16 are not connected internally on these
devices; consequently connections to these terminals will not affect
circuit operation.•
•
•
•
•
•

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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648

1
16
SOIC–16
D SUFFIX
CASE 751B

High Source and Sink Currents
High–to–Low Level Converter
Supply Voltage Range = 3.0 V to 18 V
VIN can exceed VDD
Meets JEDEC B Specifications
Improved ESD Protection On All Inputs

Parameter

TSSOP–16
DT SUFFIX
CASE 948F

Value

Unit

DC SupplyVoltage Range

–0.5 to +18.0

Vin

Input Voltage Range
(DC or Transient)

–0.5 to +18.0

SOEIAJ–16
F SUFFIX
CASE 966

V
V

Output Voltage Range
(DC or Transient)

14
0xxB
ALYW
16

VDD

Vout

140xxB
AWLYWW
1 16

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol

MC140xxBCP
AWLYYWW

–0.5 to VDD + 0.5

V

Iin

Input Current
(DC or Transient)per Pin

±10

mA

Iout

Output Current
(DC or Transient) per Pin

±45

mA

PD

Power Dissipation,
per Package (Note 3.)
(Plastic)
(SOIC)

xx
A
WL, L
YY, Y
WW, W

1
MC140xxB
ALYW

1
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week

ORDERING INFORMATION
Device

Package

Shipping

MC14049BCP

PDIP–16

2000/Box

MC14049BDSOIC–16

2400/Box

SOIC–16

2500/Tape & Reel

SOEIAJ–16

See Note 1.

mW
825
740

TA

Ambient Temperature Range

–55 to +125

°C

MC14049BDR2

Tstg

Storage Temperature Range

–65 to +150

°C

MC14049BF

TL

Lead Temperature
(8–Second Soldering)

260

°C

MC14050BCP

PDIP–16

2000/Box

2. Maximum Ratings are those values beyond which damage tothe device
may occur.
3. Temperature Derating: See Figure 3.

MC14050BD

SOIC–16

2400/Box

MC14050BDR2

SOIC–16

2500/Tape & Reel

This device contains protection circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the VSS pin only. Extra
precautions must be taken to avoid applications of any voltage higher than themaximum rated voltages to this high–impedance circuit. For proper operation, the
ranges VSS ≤ Vin ≤ 18 V and VSS ≤ Vout ≤ VDD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.

MC14050BDTEL

TSSOP–16 2000/Tape & Reel

MC14050BF

SOEIAJ–16

See Note 1.

MC14050BFEL

SOEIAJ–16

See Note1.

© Semiconductor Components Industries, LLC, 2000

August, 2000 – Rev. 4

1

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

Publication Order Number:
MC14049B/D

MC14049B, MC14050B
PIN ASSIGNMENT
VDD

1

16

NC

OUTA

2

15

OUTF

INA

3

14

INF

OUTB

4

13

NCINB

5

12

OUTE

OUTC

6

11

INE

INC

7

10

OUTD

VSS

8

9

IND

LOGIC DIAGRAM

MC14049B

MC14050B

3

2

3

2

5

4

5

4

7

6

7

6

9

10

9

10

11

12

11

12

14

15

14

15
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1

NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1

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