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Phase Locked Loops for High-Frequency Receivers and Transmitters—Part 3
Mike Curtin and Paul O’Brien
The first part of this series introduced phase-locked loops (PLLs), described basic architectures and principles of operation. It also included an example of where a PLL is used in communications systems. In the second part of the series, critical performance specifications, like phase noise,reference spurs, and output leakage, were examined in detail, and their effects on system performance were considered. In this, the last part of the series, we will deal with some of the main building blocks that go to make up the PLL synthesizer. We will also compare integer-N and fractional-N architectures. The series will end with a summary of VCOs currently available on the market and a listingof the Analog Devices family of synthesizers.

V+

HI

D1

Q1

UP

U4

P1

U1
+IN CLR1 OUT DELAY

U3

HI

CLR2 DOWN D2 Q2

N1

U2
–IN V– (0V)

Figure 1. Typical PFD using D-type flip flops. Consider now how the circuit behaves if the system is out of lock and the frequency at +IN is much higher than the frequency at –IN, as exemplified in Figure 2.
+IN

PLLSynthesizer Basic Building Blocks A PLL synthesizer can be considered in terms of several basic building blocks. Already touched upon, they will now be dealt with in greater detail:
Phase-Frequency Detector (PFD) Reference Counter (R) Feedback Counter (N)

–IN OUT

Figure 2. PFD waveforms, out of frequency and phase lock. Since the frequency at +IN is much higher than that at –IN, the output spendsmost of its time in the high state. The first rising edge on +IN sends the output high and this is maintained until the first rising edge occurs on –IN. In a practical system this means that the output, and thus the input to the VCO, is driven higher, resulting in an increase in frequency at –IN. This is exactly what is desired. If the frequency on +IN were much lower than on –IN, the oppositeeffect would occur. The output at OUT would spend most of its time in the low condition. This would have the effect of driving the VCO in the negative direction and again bring the frequency at –IN much closer to that at +IN, to approach the locked condition. Figure 3 shows the waveforms when the inputs are frequency-locked and close to phase-lock.
+IN

The Phase-Frequency Detector (PFD) The heartof a synthesizer is the phase detector—or phasefrequency detector. This is where the reference frequency signal is compared with the signal fed back from the VCO output, and the resulting error signal is used to drive the loop filter and VCO. In a digital PLL (DPLL) the phase detector or phase-frequency detector is a logical element. The three most common implementations are :
Exclusive-or(EXOR) Gate J-K Flip-Flop Digital Phase-Frequency Detector Here we will consider only the PFD, the element used in the ADF4110 and ADF4210 synthesizer families, because—unlike the EXOR gate and the J-K flip flop—its output is a function of both the frequency difference and the phase difference between the two inputs when it is in the unlocked state. Figure 1 shows one implementation of a PFD, basicallyconsisting of two D-type flip flops. One Q output enables a positive current source; and the other Q output enables a negative current source. Assuming that, in this design, the D-type flip flop is positive-edge triggered, the states are these (Q1, Q2): 11—both outputs high, is disabled by the AND gate (U3) back to the CLR pins on the flip flops. 00—both P1 and N1 are turned off and the output,OUT, is essentially in a high impedance state. 10—P1 is turned on, N1 is turned off, and the output is at V+. 01—P1 is turned off, N1 is turned on, and the output is at V–.

–IN OUT

Figure 3. PFD waveforms, in frequency lock but out of phase lock. Since +IN is leading –IN, the output is a series of positive current pulses. These pulses will tend to drive the VCO so that the –IN signal become...