Manual Z80

Z80 Family CPU User Manual
User Manual
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ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com

Z80 CPU User’s Manual

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Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ©2002 by ZiLOG, Inc. All rights reserved. Information inthis publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OFINFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

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Table ofContents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Arithmetic Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .5 Instruction Register and CPU Control . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .7 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Memory Read Or Write . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Input or Output Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Bus Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Interrupt Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . .16 Non-Maskable Interrupt Response . . . . . . . . . . . . .. . . . . . . . . . . . . . . .17 HALT Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Power-Down Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Power-Down Release Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Interrupt Response . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .22 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Interrupt Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 CPU Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Hardware and Software Implementation Examples . ....