Power-Scalable Coherence

Power-Scalable Coherence
Stefanos Kaxiras1 and Georgios Keramidas2
1 Department of Electrical and Computer Engineering, University

of Patras, Greece - member of HIPEAC

{kaxiras@ece.upatras.gr}
2 Industrial

Systems Institute, Patras, Greece - member of HIPEAC
{keramidas@ece.upatras.gr}

Abstract-High-performance CMP designs cannot simply scale in performance using more cores,ignoring the issue of power consumption —a first-class design constraint. In the European SARC (Scalable Architecture) project we consider CMP designs to be power scalable if they show sustainable power efficiency (measured as the EDP of a target workload) as the core count is increased. Our goal is to improve power scalability of shared-memory CMPs by making directory coherence much more efficient inboth power and performance. More specifically, we eliminate two major sources of inefficiency for directory coherence protocols: invalidation traffic on writes and directory indirection for finding the writer. We use tear-off blocks (that are not registered in the directory but self-invalidate on synchronization) to eliminate invalidation and upgrade traffic. Since tear-off copies do not need togo to the directory, we use writer prediction to eliminate directory indirection and go to the writers directly. We thus achieve, at the same time, both power (network traffic reduction) and performance (read/write latency reduction) benefits. For writer prediction we use an efficient combination of instruction– and address–based predictions. We evaluate our proposal using a modified version ofthe GEMS simulator and show significant improvements in EDP over a base MESI directory protocol, improvements which increase with core count. Further extenstions can easily tie several coherence optimizations to our approach.

I. INTRODUCTION To scale application performance in the era of multicores we must rely on explicit parallelism, beyond just ILP. An important issue for advances in thisdirection, is ease of parallel programming and to this end, the shared-memory programming model offers a good starting point. However, at the same time, we cannot ignore the issue of power efficiency. Poor power-efficiency —overblown power budgets for diminishing performance gains— killed the development of ever wider ILP architectures. The danger of exploding power budgets for diminishingperformance gains is also visible in multicores: when, for example, a parallel application experiences sub-linear speed-up and/or consumes power that increases faster than the number of cores allocated to the application. Hill describes the various notions of the term scalability [24], and, in the era of multicores, it is useful to think of the scalability of a parallel program in terms ofpower-performance. An

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Figure 1. Speed-up, Normalized Core EDP, NormalizedNetwork & Cache EDP average over all SPLASH-2 and Normalized Network and Cache EDP for fft, radix and ocean-ncont.

existing metric, the Energy-Delay Product (EDP) [23] fits this purpose very well and in this work, we study the EDP scalability of parallel programs. The power efficiency (EDP) of a parallel application is shaped by three forces: • the performance scalability (speedup) of the...