Tabla de datos del cd4541b

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CD4541B
Data sheet acquired from Harris Semiconductor SCHS085

CMOS Programmable Timer High Voltage Types (20V Rating)
Description
CD4541B programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edgeclock transitions and can also be reset via the MASTER RESET input. The output from this timer is the Q or Q output from the 8th, 10th, 13th, or 16th counter stage. The desired stage is chosen using time-select inputs A and B (see Frequency Select Table). The output is available in either of two modes selectable via the MODE input, pin 10 (see Truth Table). When this MODE input is a logic “1”, theoutput will be a continuous square wave having a frequency equal to the oscillator frequency divided by 2N. With the MODE input set to logic “0” and after a MASTER RESET is initiated, the output (assuming Q output has been selected) changes from a low to a high state after 2N-1 counts and remains in that state until another MASTER RESET pulse is applied or the MODE input is set to a logic “1”.Timing is initialized by setting the AUTO RESET input (pin 5) to logic “0” and turning power on. If pin 5 is set to logic “1”, the AUTO RESET circuit is disabled and counting will not start until after a positive MASTER RESET pulse is applied and returns to a low level. The AUTO RESET consumes an appreciable amount of power and should not be used if low-power operation is desired. For reliableautomatic power-on reset, VDD should be greater than 5V. The RC oscillator, shown in Figure 2, oscillates with a frequency determined by the RC network and is calculated using:
1 f = ---------------------------------2.3 R TC C TC Where f is between 1kHz and 100kHz and R S ≥ 10k Ω and ≈ 2R TC

Features
• Low Symmetrical Output Resistance, Typically 100Ω at VDD = 15V • Built-In Low-Power RC Oscillator •Oscillator Frequency Range . . . . . . . . . . DC to 100kHz • External Clock (Applied to Pin 3) can be Used Instead of Oscillator • Operates as 2N Frequency Divider or as a SingleTransition Timer • Q/Q Select Provides Output Logic Level Flexibility • AUTO or MASTER RESET Disables Oscillator During Reset to Reduce Power Dissipation • Operates With Very Slow Clock Rise and Fall Times • Capable ofDriving Six Low Power TTL Loads, Three Low-Power Schottky Loads, or Six HTL Loads Over the Rated Temperature Range • Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • 5V, 10V, and 15V Parametric Ratings • Meets All Requirements of JEDEC Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

[ /Title (CD45 41B) /Subject (CMO SProgrammable Timer High Voltage Types (20V Rating)) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS , pdip, cerdip, mil, military, mil

Ordering Information
PART NUMBER CD4541BF CD4541BE CD4541BH CD4541BM TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld PDIP Chip 14 Ld SOIC PKG. NO. F14.3 E14.3 M14.15

Pinout
CD4541B (CERDIP, PDIP, SOIC)TOP VIEW
RTC 1 CTC 2 RS 3 NC 4 AUTO RESET 5 MASTER RESET 6 VSS 7 14 VDD 13 B 12 A 11 NC 10 MODE 9 Q/Q SELECT 8 OUTPUT

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

© Harris Corporation 1998

File Number

1378.1

1

CD4541B Functional Diagram
12 A 13 B 1 RTC 2 CTC 3 RS 5 AR 6 MR 10 MODE 9 Q/Q SELECT

8Q

VDD = PIN 14 VSS = PIN 7

Functional Block Diagram
12 13

†A †B

R N P 1 OF 3 MUX 216 OR 28 8 Q

N P 3

9

†Q/Q SELECT

†RS
2

210 213 OSC 8-STAGE COUNTER R R

†CTC †RTC
1

8-STAGE COUNTER R 10 †MODE

VDD

AUTO RESET†

5

PWR ON RESET 6 VDD = 14 VSS = 7 NC = 4, 11

VSS

† All inputs are protected by CMOS Protection Network.

MANUAL RESET†

FIGURE...
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