Calculadora en vhdl

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity RPN_Calc is 
 Port ( Clk :      in  std_logic; 
        Switches : in std_logic_vector(7 downto 0); 
        Buttons :  in  std_logic_vector(6 downto 0); 
        Result :   out std_logic_vector(7 downto 0)); 
end RPN_Calc; 

architecture Behavioral of RPN_Calc is  Signal Q0,Q1,Q2,Q3: std_logic_vector(7 downto 0) := (others=>'0'); 
 Signal S:           std_logic_vector(1 downto 0); 
 Signal S3S2S1S0:    std_logic_vector(3 downto 0); 
 Signal D,B,T:      std_logic_vector(7 downto 0); 
 signal Old_buttons: std_logic_vector(6 downto 0); 
begin 
 T      <= Switches; 
 B      <= (others=>'0');   
 Result <= Q0; 

 One_puls_detector:  process( clk) 
    variable One_pulses: std_logic_vector(6 downto 0); 
 begin 
    if rising_edge( Clk) then 
       Old_buttons <= Buttons; 
       One_pulses  := not Old_buttons and Buttons; 
      case One_pulses is 
          when "0000001" => S <= "01"; S3S2S1S0 <= "0000"; -- Enter 
          when "0000010" => S <= "10"; S3S2S1S0 <= "0000"; -- Pop 
          when"0000100" => S <= "11"; S3S2S1S0 <= "0001"; -- + 
          when "0001000" => S <= "11"; S3S2S1S0 <= "0010"; -- - 
          when "0010000" => S <= "11"; S3S2S1S0 <= "0100";-- * 
          when "0100000" => S <= "11"; S3S2S1S0 <= "1000"; -- / 
          when "1000000" => S <= "11"; S3S2S1S0 <= "1111"; -- XOR 
          when  others   => S <="00"; S3S2S1S0 <= "0000"; -- nop 
        end case; 
     end if; 
  end process; 
        
  The_RPN_Stack: 
  process( Clk) 
  begin 
     if rising_edge( Clk) then 
        case S is 
          When "00" => Null; 
           When "01" => Q3<=Q2; Q2<=Q1; Q1<=Q0; Q0<=T; 
           When "10" => Q0<=Q1; Q1<=Q2; Q2<=Q3; Q3<=B; 
           When...