Microcontrolador Motorola Hc05

An Introduction to Motorola’s 68HC05 Family of 8-Bit Microcontrollers

This presentation is a self paced tutorial of the 68HC05 family of 8-bit microcontrollers.

Table of Contents

Ç CPU Overview Ç Instruction Set Ç Addressing Modes Ç Sample HC05 Code Example Ç Smart Light Dimmer Application Example Ç Bicycling Computer Application Example Ç Other 68HC05 Family Peripherals
2 98/06/23The Tutorial starts with an architectural overview of the 68HC05 central processor unit (CPU). It covers memory organization, the CPU programmer’s model, stack pointer operation, and the 68HC05 instruction set and its addressing modes. Once learned, this knowledge is applicable to all 68HC05 devices, because they all use the same CPU. In the second part of this tutorial, two sample applicationsillustrate the use of some common 68HC05 peripherals. One of these is a smart light dimmer in which the very low cost MC68HC705KJ1 provides features not available on conventional electro-mechanical dimmers. The other is a cycling computer that uses the MC68HC705P6A to monitor rider heart rate, temperature, humidity, speed, and distance traveled. Other common 68HC05 peripherals are covered in thethird and final section of this tutorial. These provide some of the communication, timing, and display features of embedded control applications not illustrated in the previous examples.

68HC05 Memory Organization
$0000 $0020 I/O & CONTROL REGISTERS $0200 $0201 $0202 RAM $0203 $0204 $0100 $0205 $0206 $0207 $CD $11 $20 $B7 STA $11 $11 $D6 $04 $00 LDA $0400,X JSR $1120

ROM/EPROM

$xxFA $xx00BOOT ROM $xxF0 VECTORS $xxFF $xxFB $xxFC $xxFD $xxFE $xxFF

$03 $CD $02 $F0 $01 $00

IRQ

VECTOR ($03CD)

SWI VECTOR ($02F0) RESET VECTOR ($0100)

3

98/07/02

The 68HC05 is a Von Neumann computer. All storage and input/output resources are memory mapped into a single linear address space. The memory map is organized as bytes, begins at $0000, and ends at $xxFF, where, depending onfactors like ROM or EPROM array size, ‘xx’ is $03, $07, $0F, $1F, $3F, or $7F. The address space on a 68HC05 device is usually sized just large enough to contain the integrated ROM or EPROM, RAM, and control registers. The MC68HC705KJ1, for example, has a 2-Kbyte (‘xx’ equals $07) memory map containing 1240 bytes of EPROM, 64 bytes of RAM, and 14 bytes of other processor accessible resources. The68HC05 is also a Big Endian machine. A 16-bit piece of data, or word, is stored in memory with its high byte at address N and its low byte at address N + 1. This ordering applies whether the word is part of an assembled instruction (such as an index register offset), a return address residing on the stack, or the address of a service routine contained in an interrupt vector. See the examples above.68HC05 Programmer’s Model
7 6 5 4 3 2 1 0

Accumulator (A)
7 6 5 4 3 2 1 0

Index Register (X)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 1 1

Stack Pointer (SP)
5 4 3 2 1 0

15 14 13 12 11 10

9

8

7

6

Program Counter (PC)
7 6 5 4 3 2 1 0

1 1 1 H I N Z C

Condition Code Register (CCR)

Half Carry Flag Interrupt Mask Negative Flag Zero FlagCarry/Borrow Flag
4 98/07/02

The 68HC05 central processor unit (CPU) consists of an accumulator (A), an index register (X), a stack pointer (SP), a program counter (PC), and a condition code register (CCR). Data can be read from memory into the accumulator and the index register. Likewise, data can be written into memory from the accumulator and the index register. The accumulator, however, is theonly register upon which arithmetic and combinatorial logic operations can be performed. Only the index register can provide user-generated effective addresses for operands read into or written from the accumulator. Both the accumulator and the index register support bitwise shift and rotate operations. Most accumulator, index register, and memory operations affect status flags in the condition...