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VHDL MINI-REFERENCE
See the VHDL Language Reference Manual (VLRM) for Additional Details The following Mini-Reference can be divided into the following parts: Primary Design Unit Model Structure A. Entity Declaration Format B. Architecture II. Packages A. Declaration and Libraries B. Identifiers, Numbers, Strings, and Expressions C. Data Types D. Objects: Signals, Constants,and Variables E. Concurrent Statements 1) Signal Assignment 2) Process Statement 3) Block Statement 4) Procedure Statement 5) Component Instantiation 6) Concurrent Assertion 7) Generate Statement F. Sequential Statements 1) Wait Statement 2) Signal Assignment 3) Variable Assignment 4) Procedure Call 5) Conditional Statements 6) Loop Statements 7) Procedure Statement 8) Function Statement G. OtherIEEE "std.logic" Functions H. Object Attributes I. The TEXTIO Package I.

PRIMARY DESIGN UNIT MODEL STRUCTURE - Back To Top
Each VHDL design unit comprises an "entity" declaration and one or more "architectures". Each architecture defines a different implementation or model of a given design unit. The entity definition defines the inputs to, and outputs from the module, and any "generic"parameters used by the different implementations of the module.

Entity Declaration Format - Back To Top
http://www.eng.auburn.edu/department/ee/mgc/vhdl.html 04/03/02

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entity name is port( port definition list );-- input/output signal ports generic( generic list); -- optional generic list end name;

Port declaration format: port_name: mode data_type; The mode of a port definesthe directions of the singals on that pirt, and is one of: in, out, buffer, or inout. Port Modes: An in port can be read but not updated within the module, carrying information into the module. (An in port cannot appear on the left hand side of a signal assignment.) An out port can be updated but not read within the module, carrying information out of the module. (An out port cannot appear on theright hand side of a signal assigment.) A buffer port likewise carries information out of a module, but can be both updated and read within the module. An inout port is bidirectional and can be both read and updated, with multiple update sources possible. NOTE: A buffer is strictly an output port, i.e. can only be driven from within the module, while inout is truly bidirectional with drivers bothwithin and external to the module.
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Example
entity counter is port (Incr, Load, Clock: in Carry: out Data_Out: buffer Data_In: in end fulladder; bit; bit; bit_vector(7 downto 0); bit_vector(7 downto 0));

Generics allow static information to be communicated to a block from its environment for all architectures of a design unit. These include timing information (setup, hold, delay times),part sizes, and other parameters. Example
entity and_gate is port(a,b: in bit; c: out bit); generic (gate_delay: time := 5ns); end and_gate;

Architecture - Back To Top
An architecture defines one particular implementation of a design unit, at some desired level of abstraction. http://www.eng.auburn.edu/department/ee/mgc/vhdl.html 04/03/02

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architecture arch_name ofentity_name is ... declarations ... begin ... concurrent statements ... end

Declarations include data types, constants, signals, files, components, attributes, subprograms, and other information to be used in the implementation description. Concurrent statements describe a design unit at one or more levels of modeling abstraction, including dataflow, structure, and/or behavior.
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BehavioralModel: No structure or technology implied. Usually written in sequential, procedural style. Dataflow Model: All datapaths shown, plus all control signals. Structural Model: Interconnection of components.

VHDL PACKAGES - Back To Top
A VHDL package contains subprograms, constant definitions, and/or type definitions to be used throughout one or more design units. Each package comprises a...