74S374

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MC54/74F374 OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
The MC54/74F374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs forbus oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.

OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
FAST™ SCHOTTKY TTL

• • • •

Edge-triggeredD-Type Inputs Buffered Positive Edge-triggered Clock 3-State Outputs for Bus-Oriented Applications ESD > 4000 Volts

CONNECTION DIAGRAM (TOP VIEW)
VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O412 CP 11
20 1

J SUFFIX CERAMIC CASE 732-03

N SUFFIX PLASTIC CASE 738-03
20 1

1 OE

2 O0

3 D0

4 D1

5 O1

6 O2

7 D2

8 D3

9 O3

10 GND
20

FUNCTION TABLE
Inputs DnH L X
H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance

1

DW SUFFIX SOIC CASE 751D-03

Outputs CP OE L L X H On H L Z

ORDERING INFORMATION
MC54FXXXJ CeramicMC74FXXXN Plastic MC74FXXXDW SOIC

LOGIC SYMBOL

3

4

7

8 13 14 17 18

11 1

D0 D1 D2 D3 D4 D5 D6 D7 CP OE O0 O1 O2 O3 O4 O5 O6 O7 2 5 6 9 12 15 16 19

VCC = PIN 20 GND = PIN 10FAST AND LS TTL DATA 4-170

MC54/74F374

FUNCTIONAL DESCRIPTION The F374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state true outputs. The buffered clock andbuffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP)transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OEinput does not affect the state of the flip-flops.

LOGIC DIAGRAM

D0 CP CP D Q Q

D1

D2

D3

D4

D5

D6

D7

CP D Q Q

CP D Q Q

CP D Q Q

CP D Q Q

CP D Q Q

CP D Q Q...
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