Buffer Triestate 8 Bits

SN74LS373 SN74LS374 Octal Transparent Latch with 3-State Outputs; Octal D-Type Flip-Flop with 3-State Output
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears onthe bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN74LS374 is manufactured using advanced LowPower Schottky technology and is compatible with all ON Semiconductor TTL families.
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LOW POWER SCHOTTKY

• • • • • • •

Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp Diodes Limit High SpeedTermination Effects

20 1

PLASTIC N SUFFIX CASE 738

GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 – 2.6 24 Unit V °C mA mA

20 1

SOIC DW SUFFIX CASE 751D

ORDERING INFORMATION
Device SN74LS373N SN74LS373DW SN74LS374N SN74LS374DW Package 16 Pin DIP16 Pin 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel 1440 Units/Box 2500/Tape & Reel

© Semiconductor Components Industries, LLC, 1999

1

December, 1999 – Rev. 6

Publication Order Number: SN74LS373/D

SN74LS373 SN74LS374
CONNECTION DIAGRAM DIP (TOP VIEW) SN74LS373
VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 LE 11 VCC 20 O7 19 D7 18 D6 17

SN74LS374
O6 16 O515 D5 14 D4 13 O4 12 CP 11

1 OE

2 O0

3 D0

4 D1

5 O1

6 O2

7 D2

8 D3

9 O3

10 GND

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

1 OE

2 O0

3 D0

4 D1

5 O1

6 O2

7 D2

8 D3

9 O3

10 GND

LOADING (Note a) PIN NAMES D0 – D7 LE CP OE O0 – O7 Data Inputs Latch Enable (Active HIGH) Input Clock(Active HIGH Going Edge) Input Output Enable (Active LOW) Input Outputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L.

NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

TRUTH TABLE LS373
Dn H L X X LE H H L X OE L L L H On H L Q0 Z* Dn H L X X

LS374
LE OE L L H On H L Z*

H = HIGH Voltage Level L = LOW Voltage Level X =Immaterial Z = High Impedance * Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).

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2

SN74LS373 SN74LS374
LOGIC DIAGRAMS SN74LS373
3 4 7 8 13 14 17 18

D0 D LATCH ENABLE LE 11 OE Q G

D1 D Q G

D2 D Q G

D3 D Q G

D4 D Q G

D5 D Q G

D6 D Q G

D7 D Q G

VCC = PIN 20 GND = PIN 10 = PIN NUMBERS

1

O0
2 5

O1
6

O29

O3
12

O4
15

O5
16

O6
19

O7

SN74LS374
3 11 4 7 8 13 14 17 18

D0 CP D Q Q CP D Q Q

D1 CP D Q Q

D2 CP D Q Q

D3 CP D Q Q

D4 CP D Q Q

D5 CP D Q Q

D6 CP D Q Q

D7

CP

OE
1 2

O0
5

O1
6

O2
9

O3
12

O4
15

O5
16

O6
19

O7

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIHVIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.4 – 0.65 3.1 0.25 VO OL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 0.35 Output Off Current HIGH Output Off Current LOW Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current – 30 0.5 20 – 20 20 0.1 – 0.4 – 130 40 V µA µA µA mA mA mA mA IOL = 24 mA 0.4 Min...