Computadoras
User Manual
UM008005-0205
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
Z80 CPU User’s Manual
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UM008005-0205
Z80 CPU User’s Manual
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RevisionHistory
Each instance in Table 1 reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table.
Table 1. Revision History of this Document Revision Level Section
Date
Description
Page # 176,177, 178
December 04 2004
Z80 Instruction Corrected discrepancies in the bit Set patterns for IM 0, IM 1 and IM 2 instructions. Z80Instruction Set, CPU Instruction Description Corrected illustration for the Rotate and Shift Group RLCA instruction. Also corrected the hex code for the RLCA instruction on page 63.
February 2005
05
190, 63
Chapter Title
UM008005-0205
Z80 CPU User’s Manual iv
UM008005-0205
PRELIMINARY DRAFT v1.0
Chapter Title
Z80 CPU User’s Manual
v
Table of Contents
RevisionHistory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Arithmetic LogicUnit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Instruction Register and CPU Control . . . . . . . . . . . . . . . . . . . . . . 6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Functions . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .7 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Memory Read Or Write . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .13 Input or Output Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bus Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . .15 Interrupt Request/Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . .16 Non-Maskable Interrupt Response . . . . . . . . . . . . . . . . . . . . . . . .17 HALT Exit . . . . . ....
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