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PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS
The SN54 / 74LS190 is a synchronous UP/ DOWN BCD Decade (8421) Counter and the SN54/ 74LS191 is a synchronous UP / DOWN Modulo-16 Binary Counter. State changes of the counters are synchronous with the LOW-to-HIGH transition of the Clock Pulse input. An asynchronous Parallel Load (PL) input overrides counting andloads the data present on the Pn inputs into the flip-flops, which makes it possible to use the circuits as programmable counters. A Count Enable (CE) input serves as the carry / borrow input in multi-stage counters. An Up / Down Count Control (U/D) input determines whether a circuit counts up or down. A Terminal Count (TC) output and a Ripple Clock (RC) output provide overflow/underflow indicationand make possible a variety of methods for generating carry / borrow signals in multistage counter applications.

SN54/74LS190 SN54/74LS191

PRESETTABLE BCD/ DECADE UP/ DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/ DOWN COUNTERS
LOW POWER SCHOTTKY

J SUFFIX CERAMIC CASE 620-09
16 1

• • • • • • • •

Low Power . . . 90 mW Typical Dissipation High Speed . . . 25 MHz Typical Count FrequencySynchronous Counting Asynchronous Parallel Load Individual Preset Inputs Count Enable and Up/ Down Control Inputs Cascadable Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW)
V CC 16 P 0 15 CP 14 RC 13 TC 12 PL 11 P 2 10 P 3 9

16 1

N SUFFIX PLASTIC CASE 648-08

16 1

D SUFFIX SOIC CASE 751B-03

ORDERING INFORMATION
NOTE: The Flatpak version hasthe same pinouts (Connection Diagram) as the Dual In-Line Package.

SN54LSXXXJ SN74LSXXXN SN74LSXXXD

Ceramic Plastic SOIC

1 P 1

2 Q 1

3 Q 0

4 CE

5 U/D

6 Q 2

7 Q 3

8 GND

LOGIC SYMBOL
11 15 1 10 9

PIN NAMES

LOADING (Note a) HIGH LOW 0.7 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 5 (2.5) U.L.
PL 5 U/D P 0 P P 1 2 P 3 RC 13

CE CPU/D PL Pn Qn RC TC

Count Enable (Active LOW) Input Clock Pulse (Active HIGH going edge) Input Up/Down Count Control Input Parallel Load Control (Active LOW) Input Parallel Data Inputs Flip-Flop Outputs (Note b) Ripple Clock Output (Note b) Terminal Count Output (Note b)

1.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 10 U.L.

4 14

CE CP Q 0 Q 1 Q 2 Q 3 TC 12

3

2

67

V = PIN 16 CC GND = PIN 8

NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges.

FAST AND LS TTL DATA 5-341

SN54/74LS190 • SN54/74LS191
STATE DIAGRAMS

0

1

2

3

4

0

1

2

3

4

LS190
UP: 15 5 DOWN: TC = Q0 TC = Q0

⋅ Q3 ⋅ (U/D) ⋅ Q1⋅ Q2 ⋅ Q3 ⋅ (U/D)

15

5

14

6 UP: DOWN:

LS191
TC = Q0

⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U/D) TC = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ (U/D)

14

6

13

7 COUNT UP

13

7

12

11

10

9

8

COUNT DOWN

12

11

10

9

8

LS190

LS191

LOGIC DIAGRAMS

CP
14

U/D
5

P0
15

CE
4

P1
1

P2
10

P3
9

PL
11

J

CLOCK

K

J

CLOCK

K

J

CLOCKK

J

CLOCK

K

PRESET Q

CLEAR Q

PRESET Q

CLEAR Q

PRESET Q

CLEAR Q

PRESET Q

CLEAR Q

13

12

3

2

6

7

RC

TC

Q0

Q1

Q2

Q3

VCC = PIN 16 GND = PIN 8 = PIN NUMBERS

DECADE COUNTER LS190

FAST AND LS TTL DATA 5-342

SN54/74LS190 • SN54/74LS191

LOGIC DIAGRAMS (continued)
CP
14

U/D
5

P 0
15

CE
4

P 1
1

P 2
10P 3
9

PL
11

J

CLOCK

K

J

CLOCK

K

J

CLOCK

K

J

CLOCK

K

PRESET Q

CLEAR Q

PRESET Q

CLEAR Q

PRESET Q

CLEAR Q

PRESET Q

CLEAR Q

13

12

3

2

6

7

RC

TC

Q 0

Q 1

Q 2

Q 3

V = PIN 16 CC GND = PIN 8 = PIN NUMBERS

BINARY COUNTER LS191

FAST AND LS TTL DATA 5-343

SN54/74LS190 • SN54/74LS191...