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Features
• Fast Read Access Time – 150 ns • Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes – Internal Control Timer Fast Write Cycle Times – Page Write Cycle Time: 3 ms or 10 ms Maximum – 1 to 64-byte Page Write Operation Low Power Dissipation – 50 mA Active Current – 200 µA CMOS Standby Current Hardware and Software Data Protection DATA Polling for End of WriteDetection High Reliability CMOS Technology – Endurance: 104 or 105 Cycles – Data Retention: 10 Years Single 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout Full Military and Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Option





• • •

256K (32K x 8) Paged Parallel EEPROM AT28C256

• • • • •

1. Description
The AT28C256is a high-performance electrically erasable and programmable readonly memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 150 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 200 µA. The AT28C256 is accessed like a StaticRAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latcheddata using an internal control timer. The end of a write cycle can be detected by DATA Polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s AT28C256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. Anoptional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.

0006M–PEEPR–12/09

2. Pin Configurations
Pin Name A0 - A14 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect

2.1

28-leadTSOP Top View
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2

2.3

32-pad LCC, 28-lead PLCC Top View
A7 A12 A14 DC VCC WE A13

Note:

PLCC package pins 1 and 17 are Don’t Connect.

2.2

28-lead PGA Top View

2.4

28-lead Cerdip/PDIP/Flatpack/SOIC –Top View
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3

2

AT28C256
0006M–PEEPR–12/09

I/O1 I/O2 GND DC I/O3 I/O4 I/O5

14 15 16 17 18 19 20

A6 A5 A4 A3 A2 A1 A0 NC I/O0

5 6 7 8 9 10 11 12 13

4 3 2 1 32 31 30

29 28 27 26 25 24 23 22 21

A8A9 A11 NC OE A10 CE I/O7 I/O6

AT28C256
3. Block Diagram

4. Device Operation
4.1 Read
The AT28C256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designersflexibility in preventing bus contention in their system.

4.2

Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion....
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