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64K NV SRAM with Phantom Clock

§ Real time clock keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years § 8K x 8 NV SRAM directly replaces volatile static RAM or EEPROM § Embedded lithium energy cell maintains calendar operation and retains RAM data § Watch function is transparent to RAM operation § Monthand year determine the number of days in each month; valid up to 2100 § Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time § Standard 28–pin JEDEC pinout § Full ±10% operating range § Operating temperature range 0°C to 70°C § Accuracy is better than ±1 minute/month @ 25°C § Over 10 years of data retention in the absence of power §Available in 120, 150 and 200 ns access time

RST A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3

28-Pin Encapsulated Package 720-Mil Extended



DS1243Y–XXX –120 120 ns access –150150 ns access 200 ns access


– Address Inputs – Chip Enable – Ground – Data In/Data Out – Power (+5V) – Write Enable – Output Enable – No Connect – Reset


The DS1243Y 64K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 8192 words by 8 bits) with a built–in real time clock. The DS1243Y has a self–contained lithium energy source andcontrol circuitry which constantly monitors VCC for an out–of–tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent corrupted data in both the memory and real time clock.

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The Phantom Clock provides timekeeping information including hundredths ofseconds, seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap years. The Phantom Clock operates in either 24–hour or 12–hour format with an AM/PM indicator.

The DS1243Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (ChipEnable) is active (low). The unique address specified by the 13 address inputs (A0–A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times and states are also satisfied. If OE and CE access times are notsatisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than address access.

The DS1243Y is in the write mode whenever the WE and CE signals are in the active (low) state after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start ofthe write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has beenenabled ( CE and OE active) then WE will disable the outputs in t ODW from its falling edge.

The DS1243Y provides full functional capability for VCC greater than VTP and write protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAM constantly monitors VCC. Should the supply voltage decay, the RAM...
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