Antonio Zenteno, Roberto G´ mez, Victor Champac o Electronic Engineering Department National Institute for Astrophysics, Optics and Electronics - INAOE P.O. Box 51 and 216 72000 Puebla, Pue., Mexico
Abstract— In this work, the possibilities to use body biasing to enhance the testability on full interconnection open defects andinterconnection resistive opens is explored. Body biasing allows to increase the threshold voltage of the Nmos and Pmos transistors. This property is used to enhance the detectability of these defects. Analytical equations considering body biasing voltages are developed to determine the detectability of full interconnection opens. Our initial results indicates that the testability of fullinterconnection opens increases. For resistive interconnection the delay also increases. Index Terms— Resistive opens, full opens, adaptive body bias, logic test, delay.
I. I NTRODUCTION The increment of testability under full and resistive opens using body bias is presented. Opens in vias-contacts ,  are likely to occur. The number of vias-contacts is high in actual integrated circuits due to the manymetal levels , . In damascene-copper process vias and metal are patterned and etched prior to the additive metalization. Because this micromasking during the next lithography step can occur . The open density in copper shows a higher value than those found in aluminum . Random particle induced-contact defects is the main test target in production testing . In addition, silicidedopens can occur due to excess anneal during manufacturing . It has been found that some resistive opens could be hard to detect. Break defects have been found to be an important contributor of test escapes . The behavior of ﬂoating connected gates due to an interconnection open has been investigated since the late eighties    . It has been found that some circuits with thesedefects work logically correctly at low frequencies, but fail at higher frequencies  . Other researchers have observed a stuck-at behavior and negligible quiescent current values for an inverter with a given double ﬂoating gate defect . The parasitic capacitances related to the ﬂoating node determines the behavior of the defective gate   . In addition, tunneling effects have been foundacross the break for small opens  . The trapped charge on the ﬂoating gate during fabrication process may inﬂuence signiﬁcantly the behavior of interconnection opens  . Needham et al.  have found via failures at postproduction for Pentium MMX ICs only when the simulated
This work was supported by CONACYT/Mexico.
resistance was greater than 830KΩ. They have found that someopen defects were detected only when appropriate stress conditions (temperature, voltage, frequency) were applied. Baker et al.  have investigated the use of delay testing to test resistive opens. They have found that the resolution of delay fault testing impact the detectability of these defects. In addition, the process parameter variation must be taken into account to deﬁne the pass/faillimits . Ferguson et al. have estimated the probability of interconnection opens under stuckat test . Figueras et al. have characterized resistive opens under crosstalk in order to predict and to detect the behavior caused by a defect . Chao et al.  have proposed to use low temperature testing to test silicided open defects. Low voltage test has been proposed to detect opens and weak CIs  . Low voltages as 2Vth and 2.5Vth have been used by  . Both to reduce leakage currents and to compensate process variations, adaptive body bias to reduce leakage currents has been currently used     . Leakage currents are reduced by changing the threshold voltage of Nmos and Pmos transistors. Usually body bias is separately used in Pmos (forward body...