Informativo

SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independentof rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. LOGIC DIAGRAM

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOPLOW POWER SCHOTTKY

SET (SD) 5(11) CLEAR (CD) 1(15) CLOCK 4(12)

Q 6(10)

J SUFFIX CERAMIC CASE 620-09
16 1

J 2(14) K 3(13)

Q 7(9)

16 1

N SUFFIX PLASTIC CASE 648-08

16

MODESELECT — TRUTH TABLE
INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset) L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H H q qL Q L H H L q q H OUTPUTS

1

D SUFFIX SOIC CASE 751B-03

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

LOGIC SYMBOL
5 2 4 3 J SD Q CP K C Q D 1 VCC = PIN 16GND = PIN 8 11 6 14 J SD Q 12 CP 7 13 K C Q D 15 9 10

* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H, h =HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the LOW to HIGH clocktransition.

FAST AND LS TTL DATA 5-1

SN54/74LS109A
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current —Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 0.4 4.0 8.0 Unit V °C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwisespecified)
Limits S b l Symbol VIH VIL VIK VOH P Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage O V l 54 74 54, 74 VOL Output LOW Voltage 74 Input HIGH...