Sadfsdfsdfsdaf

Solo disponible en BuenasTareas
  • Páginas : 32 (7781 palabras )
  • Descarga(s) : 0
  • Publicado : 29 de agosto de 2012
Leer documento completo
Vista previa del texto
ADC0802, ADC0803
ADC0804

SEMICONDUCTOR

8-Bit µP Compatible
A/D Converters

December 1993

Features

Description

• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required

The ADC0802 family are CMOS 8-Bit successive approximation A/D converters which use a modified potentiometric
ladder and are designed to operate with the 8080A control
bus via three-state outputs.These converters appear to the
processor as memory locations or I/O ports, and hence no
interfacing logic is required.

• Conversion Time < 100µs
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs

The differential analog voltage input has good commonmode-rejection and permits offsetting the analog zero-inputvoltage value.In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8-Bits of resolution.

• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• 0V to 5V Analog Voltage Input Range (Single + 5V Supply)
• No Zero-Adjust Required

Ordering Information
PART NUMBER
ADC0802LCN
ADC0802LCDERROR
1

± /2 LSB

EXTERNAL CONDITIONS

TEMPERATURE RANGE
o

VREF/2 = 2.500 VDC (No Adjustments)

0 C to +70 C

3

o

± /4 LSB

ADC0802LD
ADC0803LCN

o

ADC0803LCD
ADC0802LCWM
ADC0803LD
ADC0804LCN
ADC0804LCD

± /2 LSB
3

± /4 LSB

-55 C to +125 C
VREF/2 Adjusted for Correct Full-Scale
Reading

20 Lead Ceramic DlP

o

0 C to +70 C

20 Lead Plastic DIPo

o

20 Lead Ceramic DlP

o

o

20 Lead SOIC (W)

-40 C to +85 C

±1 LSB

-40 C to +85 C
o

±1 LSB
±1 LSB

20 Lead Ceramic DlP

o

o

PACKAGE
20 Lead Plastic DIP

o

-40 C to +85 C

±1 LSB
1

o

o

-55 C to +125 C
o

VREF/2 = 2.500 VDC (No Adjustments)

0 C to +70 C
o

±1 LSB

Pinout

20 Lead Ceramic DlP

o

20 Lead Plastic DIP

o-40 C to +85 C

20 Lead Ceramic DlP

Typical Application Schematic

ADC0802, ADC0803, ADC0804
(PDIP, CDIP)
TOP VIEW

RD

2

19 CLK R

WR

3

18 DB0 (LSB)

CLK IN

4

17 DB1

INTR

5

16 DB2

VIN (+)

6

15 DB3

RD
WR

5

20 V+ OR VREF

INTR

11
ANY
µPROCESSOR

µP BUS

1

CS

2
3

CS

1

12
13
14
15
16

VIN (-)

7

14 DB417

AGND

8

13 DB5

18

VREF/2

9

V+ 20
CLK R 19
CLK IN 4

+5V

150pF

10K

DB7
DB6
DB5
DB4

VIN (+)

6
7

DB3

VIN (-)

DB2

AGND

8

DB1

VREF/2

9

DIFF
INPUTS

8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE

12 DB6

DGND 10

DB0

DGND 10

11 DB7 (MSB)

CAUTION: These devices are sensitive to electrostaticdischarge. Users should follow proper I.C. Handling Procedures.
Copyright

VREF/2

© Harris Corporation 1993

5-3

File Number

3094

ADC0802, ADC0803, ADC0804
Functional Diagram

RD
CS
WR

2

READ

1
3

SET

“1” = RESET SHIFT REGISTER
“0” = BUSY AND RESET STATE

Q

RESET

INPUT PROTECTION
FOR ALL LOGIC INPUTS

CLK R
19

CLK

INPUT
CLK A

CLK IN

TOINTERNAL
CIRCUITS

G1

RESET

4
CLK OSC

D

BV = 30V

CLK
GEN CLKS

DFF1
Q

START F/F

10
DGND

START
CONVERSION

CLK B
MSB
20
V+
(VREF)

VREF/2

LADDER
AND
DECODER

SUCCESSIVE
APPROX.
REGISTER
AND LATCH

9

D
8-BIT
SHIFT
REGISTER

IF RESET = “0”

R
RESET

AGND

DAC
VOUT

8

LSB

INTR F/F

Q

CLK A

V+

D

VIN (+)

VIN(-)

6

+



-

DFF2

COMP

Q

+

-

Q
XFER

TRI-STATE
OUTPUT LATCHES

7

G2

SET
5

LSB

MSB

CONV. COMPL.
11 12 13 14 15 16 17 18
8 X 1/f
DIGITAL OUTPUTS
TRI-STATE CONTROL
“1” = OUTPUT ENABLE

5-4

INTR

Specifications ADC0802, ADC0803, ADC0804
Absolute Maximum Ratings

Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . ....
tracking img