According to the given specifications of the developing system, the microarchitecture of the superscalar and out of order execution processor could be divided in the next mainmodules:
* IC (Instruction Cache)
* IFQ (Instruction Fetch Queue)
* RegFile (RegisterFile)
* RST (Register Status Table)
* TAG FIFO
* Dispatch Control
* Load/Store Queue
* ALU Execution Unit
* Multiplication Execution Unit
* Division Execution Unit
* Data Cache
* Issue Unit
All these modules include several FunctionalAreas which are specified in the next section. The Functional Areas are classified according to their corresponding module.
IC (Instruction Cache)
FA-01: BRAM, 64X128(256 Instructions).
FA-02: Readcontrol signal (Active High).
FA-03: 32 bit Address input.
FA-04: Abort read input signal.
FA-05: Read Data valid indication.
IFQ (Instruction Fetch Queue)
FA-07: Read (Pop) 32bits.
FA-08: Write (Push) 128 bits.
FA-09: Full Indication.
FA-10: Empty Indication.
FA-11: FIFO Flush operation.
FA-12: Program Counter out signal.
FA-13: Jump or branch address input.
FA-14:Jump or branch valid input.
FA-15: Instruction Bypass operation for each signal.
RegFile (Register File)
FA-16: 1 Read port for RS source register.
FA-17: 1 Read port for RD source register.
FA-18:1 32 bit one hot encoded write port.
FA-19: Read priority for CDB publications over register read data.
RST (Resgister Status Table)
FA-20: 1 Write port for writing the TAG for the dispatchedinstruction.
FA-21: 1 Write port for cleaning the TAG published by CDB.
FA-22: 1 Read port for the RS register in the dispatched instruction.
FA-23: 1 Read port for the RT register in the dispatchedinstruction.
FA-24: TAG update from CDB publications.
FA-25: 0-63 FIFO Initialization values.
FA-24: FIFO Full at initialization.
FA-25: TAGOUT output signals.
FA-26: Read enable input...
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