Viterbi decoder

Proceedings of the 6th WSEAS Int. Conf. on Electronics, Hardware, Wireless and Optical Communications, Corfu Island, Greece, February 16-19, 2007

162

FPGA Implementation of Viterbi Decoder
HEMA.S, SURESH BABU.V, RAMESH P Dept of ECE, College of Engineering Trivandrum Kerala University Trivandrum, Kerala. INDIA

Abstract: - Convolutional encoding with Viterbi decoding is a powerful methodfor forward error correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. The Viterbi algorithm, which is the most extensively employed decoding algorithm for convolutional codes. In this paper, we present a field-programmable gate array implementation of Viterbi Decoder with a constraint length of 11 and a coderate of 1/3. It shows that the larger the constraint length used in a convolutional encoding process, the more powerful the code produced. Key-Words: - Convolutional codes, Viterbi Algorithm, Adaptive Viterbi decoder, Path memory, Register Exchange, Field-Programmable Gate Array (FPGA) implementation.

1 Introduction
With the growing use of digital communication, there has been an increasedinterest in high-speed Viterbi decoder design within a single chip. Advanced field programmable gate array (FPGA) technologies and welldeveloped electronic design automatic (EDA) tools have made it possible to realize a Viterbi decoder with the throughput at the order of Giga-bit per second, without using off-chip processor(s) or memory. The motivation of this thesis is to use VHDL, Synopsyssynthesis and simulation tools to realize a Viterbi decoder having constraint length 11 targeting Xilinx FPGA technology.[5] The Viterbi algorithm develops as an asymptotically optimal decoding algorithm for convolutional codes. It is nowadays commonly using for decoding block codes. Viterbi Decoding has the advantage that it has a fixed decoding time. It is well suited to hardware decoder
Hema S. isM.Tech scholar with the Department of ECE, College of Engineering Trivandrum.E-mail: hemarajen@gmail.com Suresh Babu V. is with the Department of ECE, College of Engineering Trivandrum.E-mail:vsb_sreeragam@yahoo.co.in Ramesh P is with the Dept of ECE,,Munnar Engineering. Email : ramp1718009@rediffmail.com

implementation.Viterbi decoding of convolutional codes found to be efficient and robust.Although the viterbi algorithm is, simple it requires O(2n-k) words of memory, where n is the length of the code words and k is the message length, so that n − k is the number of appended parity bits. In practical situations, it is desirable to select codes with the highest minimum Hamming distance that decodes within a specified time and an increased minimum Hamming distance d min implies anincreased number of parity bits. Our viterbi decoder necessarily distributes the memory required evenly among processing elements [1].

2. Convolutional Code
2.1 Convolutional Encoding Convolutional code is a type of error-correcting code in which each (n≥m) m-bit information symbol (each mbit string) to be encoded is transformed into an n-bit symbol, where m/n is the code rate (n≥m) and theProceedings of the 6th WSEAS Int. Conf. on Electronics, Hardware, Wireless and Optical Communications, Corfu Island, Greece, February 16-19, 2007

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transformation is a function of the last k information symbols, where K is the constraint length of the code. To convolutionally encode data, start with k memory registers, each holding 1 input bit. Unless otherwise specified, all memory registersstart with a value of 0.The encoder has n modulo-2 adders, and n generator polynomials—one for each adder (see figure1).An input bit m1 is fed into the leftmost register. Using the generator polynomials and the existing values in the remaining registers, the encoder outputs n bits [1].

Existing high-speed architectures use one processor per recursion equation. The main drawback of these...