A memory hierarchy for high-performance and energy-aware reconfigurable systems

A memory hierarchy for high-performance and energy-aware reconfigurable systems

Abstract
Run-time reconfigurable resources present many of the features demanded by next generation embedded systems such as high-performance, flexibility and reusability. In addition, many emerging reconfigurable architectures have been optimised for low-power. However, carrying out run-time reconfigurationsoften involves a costly reconfiguration overhead both in execution-time and energy consumption. In our previous work we only deal with the execution-time overhead. In this paper, we have significantly extended our approach in order to reduce the reconfiguration energy overhead as well. To this end, we propose a configuration memory hierarchy with a shared memory layer consisting of a module optimisedfor performance combined with a module optimised for energy-efficient accesses. For this hierarchy we have developed a mapping algorithm that decides where to load each configuration achieves significant energy savings without introducing any performance degradation.

Introduction
Embedded systems design complexity is rapidly increasing since applications are becoming more and more demandingand the users are expecting higher performance and extended battery life. Hence, designers must optimise their systems both for performance and reduced energy consumption. However, these two objectives frequently drive the design process in different directions. Thus, those optimisations that improve the system performance often lead to energy penalisations, whereas those that reduce the energyconsumption frequently lead to performance degradation.
Reconfigurable resources are powerful HW accelerators since it is possible to develop optimised configurations that take advantage of the inherent parallelism of each task. In addition they provide interesting features such as flexibility and reusability. Moreover, many emerging coarse-grain reconfigurable architectures have been designed forlow power and low energy consumption computations.
However, when analysing the performance and energy consumption of reconfigurable resources, it is often assumed that configurations are already loaded. Hence, only ideal results are presented. Nevertheless, a main contribution of reconfigurable resources over ASICs is the run-time flexibility they provide. Thus, new configurations can be loadedat run-time in order to adapt the system to new situations. This feature is especially interesting to deal with current multimedia applications, such as digital video and 3D games, since they exhibit highly dynamic and non-deterministic run-time behaviour, as well as a very variable workload. However, in order to efficiently tackle this dynamism, very frequent reconfigurations are demanded, andthese reconfigurations will have a clear impact both in performance and energy consumption. For example, current multimedia standards, like MPEG-4 [1], support digital video and 3D-game applications where the number and type of the objects to decode and visualize can change at run-time from one frame to another. Moreover, to reach the standard quality level, the system must be able to decode andvisualize a frame in less than 33 ms. Hence, if the decoding computations are executed in reconfigurable resources, it is likely that the system will need to carry out reconfigurations every few milliseconds in order to adapt itself to all the variations in the number and type of the objects to decode. Clearly, carrying out these reconfigurations with conventional solutions will generate some delaysin the system execution. Moreover, loading a new configuration involves a large amount of read/write operations with the consequent energy penalisation.
In this paper we propose a low-energy/high-performance configuration memory hierarchy that can be used to provide fast reconfigurations when they are especially critical for the system performance and, at the same time, reduce significantly...