Avr Set De Intrucciones

Instruction Set Nomenclature
Status Register (SREG)
SREG: C: Z: N: V: S: H: T: I: Status Register Carry Flag Zero Flag Negative Flag Two’s complement overflow indicator N ⊕ V, For signed tests Half Carry Flag Transfer bit used by BLD and BST instructions Global Interrupt Enable/Disable Flag

8-bit Instruction Set

Registers and Operands
Rd: Rr: R: K: k: b: s: X,Y,Z: Destination (andsource) register in the Register File Source register in the Register File Result after instruction is executed Constant data Constant address Bit in the Register File or I/O Register (3-bit) Bit in the Status Register (3-bit) Indirect Address Register (X=R27:R26, Y=R29:R28 and Z=R31:R30) A: q: I/O location address Displacement for direct addressing (6-bit)

Rev. 0856I–AVR–07/10

I/O RegistersRAMPX, RAMPY, RAMPZ
Registers concatenated with the X-, Y-, and Z-registers enabling indirect addressing of the whole data space on MCUs with more than 64K bytes data space, and constant data fetch on MCUs with more than 64K bytes program space.

RAMPD
Register concatenated with the Z-register enabling direct addressing of the whole data space on MCUs with more than 64K bytes data space.

EINDRegister concatenated with the Z-register enabling indirect jump and call to the whole program space on MCUs with more than 64K words (128K bytes) program space.

Stack
STACK: Stack for return address and pushed registers SP: Stack Pointer to STACK

Flags
⇔: 0: 1: -: Flag affected by instruction Flag cleared by instruction Flag set by instruction Flag not affected by instruction

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AVRInstruction Set
0856I–AVR–07/10

AVR Instruction Set
The Program and Data Addressing Modes
The AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the Program memory (Flash) and Data memory (SRAM, Register file, I/O Memory, and Extended I/O Memory). This section describes the various addressing modes supported by the AVR architecture. In thefollowing figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. To generalize, the abstract terms RAMEND and FLASHEND have been used to represent the highest location in data and program space, respectively.
Note: Not all addressing modes are present in all devices. Refer to the device spesific instructionsummary.

Register Direct, Single Register Rd Figure 1. Direct Single Register Addressing

The operand is contained in register d (Rd). Register Direct, Two Registers Rd and Rr Figure 2. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

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0856I–AVR–07/10

I/O Direct Figure 3. I/O Direct AddressingOperand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Note: Some complex AVR Microcontrollers have more peripheral units than can be supported within the 64 locations reserved in the opcode for I/O direct addressing. The extended I/O memory from address 64 to 255 can only be reached by data addressing, not I/O addressing.

Data DirectFigure 4. Direct Data Addressing
Data Space

31 OP

20 19 Rr/Rd

16

0x0000

Data Address 15 0

RAMEND

A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register.

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AVR Instruction Set
0856I–AVR–07/10

AVR Instruction Set
Data Indirect with Displacement Figure 5. Data Indirect with Displacement
Data Space0x0000 15 Y OR Z - REGISTER 0

15 OP

10 Rr/Rd

6 5 q

0

RAMEND

Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction word. Rd/Rr specify the destination or source register. Data Indirect Figure 6. Data Indirect Addressing
Data Space 0x0000 15 X, Y OR Z - REGISTER 0

RAMEND

Operand address is the contents of...