Arquitectura Itanium

7
Itanium Architecture
This chapter describes the Itanium architecture, which is the Intel 64-bit architecture.
Unlike their 32-bit architecture, this is a RISC architecture. In addition to the standard
RISC features, the Itanium incorporates several advanced architectural features such as instruction-level parallelism, register stacks, speculative execution, and predication to improveinstruction reordering. These features are discussed in detail. We conclude the chapter with a summary.
Introduction
Intel has moved from the CISC architecture used in their 32-bit processors to a RISC orientation for their 64-bit processors. The Itanium architecture defines their 64-bit processor architecture. Implementations of this architecture include the Itanium and Itanium 2 processors.
As dothe other processors discussed before, the Itanium architecture also uses the load/store architecture. Furthermore, the RISC features discussed in Chapter 3 are also present. In addition, it incorporates several advanced architectural features to improve performance. We discuss these features in detail in this chapter. More specifically, we discuss instruction-level parallelism, register stacks,speculative execution, and predication to improve instruction reordering.
The Itanium’s ISA is based on the EPIC (Explicit Parallel Instruction Computing) design philosophy. Of course, it also maintains backward compatibility to the IA-32 ISA.
EPIC design features include the following.
• Explicit Parallelism: The ISA provides necessary support for the compiler to convey information on theinstructions that can be executed in parallel. In traditional architectures, hardware extracts this Instruction-Level Parallelism (ILP) within a fairly small window of instructions (or reorder buffer). In contrast, the Itanium allows the compiler to do the job. Because ILP extraction is done in software, a more detailed analysis can be done on a much larger window at compile time.It also provideshardware support to execute instructions in parallel by reading three instructions as a bundle. The compiler packs only instructions that have no dependencies into a bundle. Thus, the processor does not have to spend time in analyzing the instruction stream to extract ILP. We present details on this and other features of the Itanium later in this chapter.
• Features to Enhance ILP: The Itanium allowsthe compiler to detect and extract ILP, therefore we can use more elaborate methods to improve ILP. Two such schemes are speculative execution and predication. Speculative execution allows high-latency load instructions to be advanced so that the latency can be masked. Branch handling is improved by using predication. In some instances, branch instructions can be completely eliminated. We presentdetails on these two techniques later.
• Resources for Parallel Execution: It is imperative that to successfully exploit the
ILP detected by the compiler, the processor should provide ample resources to execute instructions in parallel. The Itanium provides a large number of registers and functional units. It has 128 integer registers and an equal number of floating-point registers. The largenumber of registers, for example, can be effectively used to make procedure calls and returns very efficient. Most procedure calls/returns need not access memory for parameter values and local and global variables.
To summarize, the Itanium architecture improves performance by
• Increasing instruction-level parallelism by providing large register sets and a three instruction wide word;
• Hidingmemory latency by speculative loads;
• Improving branch handling by using predication; and
• Providing hardware support for efficient procedure calls and returns.
The Itanium supports both integer and floating-point data types. Integer data types can be 1, 2, 4, or 8 bytes wide. With a few exceptions, integer operations are done on 64-bit data. Furthermore, registers are always written as 64...