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MM74HC245A Octal 3-STATE Transceiver

September 1983 Revised February 1999

MM74HC245A Octal 3-STATE Transceiver
General Description
The MM74HC245A 3-STATE bidirectional buffer utilizes advanced silicon-gate CMOS technology, and is intended for two-way asynchronous communication between data buses. It has high drive current outputs which enable high speed operation even when driving largebus capacitances. This circuit possesses the low power consumption and high noise immunity usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL circuits. This device has an active LOW enable input G and a direction control input, DIR. When DIR is HIGH, data flows from the A inputs to the B outputs. When DIR is LOW, data flows from the B inputs to the Aoutputs. The MM74HC245A transfers true data from one bus to the other. This device can drive up to 15 LS-TTL Loads, and does not have Schmitt trigger inputs. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

s Typical propagation delay: 13 ns s Wide power supply range: 2–6V s Low quiescent current: 80 µA maximum (74 HC) s 3-STATE outputs for connectionto bus oriented systems s High output drive: 6 mA (minimum) s Same as the 645

Ordering Code:
Order Number MM74HC245AWM MM74HC245ASJ MM74HC245AMTC MM74HC245AN Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package(TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP

Truth Table
Control Inputs G L L H
H = HIGH Level L = LOW Level X = Irrelevant


DIR L H X B data toA bus A data to B bus Isolation

Top View

© 1999 Fairchild Semiconductor Corporation



Logic Diagram



Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC ) DC Input Voltage DIR and G pins (VIN) DC Input/Output Voltage (VIN, VOUT) Clamp Diode Current (ICD) DC Output Current, perpin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260°C 600 mW 500 mW −0.5 to +7.0V −1.5 to VCC +1.5V −0.5 to VCC +0.5V ±20 mA ±35 mA ±70 mA −65°C to +150°C

Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) OperatingTemperature Range (TA) Input Rise/Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V 1000 500 400 ns ns ns 0 −40 VCC +85 V °C 2 Max 6 Units V

Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C.DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA

(Note 4)
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 TA = 25°C Typ 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 ±0.1 ±0.5 8.0 TA = −40 to85°C TA = −55 to 125°C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 ±1.0 ±5.0 80 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 ±1.0 ±10 160 Units V V V V V V V V V V V V V V V V µA µA µA


VIN = VIH or VIL |IOUT| ≤ 6.0 mA |IOUT| ≤ 7.8 mA VOL Maximum LOW Level Output Voltage VIN = VIH or VIL |IOUT| ≤ 20 µA 2.0V 4.5V...
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