Curso vhdl sintetizable

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Writing VHDL for RTL Synthesis
Stephen A. Edwards, Columbia University December 27, 2008
The name VHDL is representative of the language itself: it is a two-level acronym that stands for VHSICHardware Description Language; V HSIC stands for very high speed integrated circuit. The language is vast, verbose, and was originally designed for modeling digital systems for simulation. As a result,the full definition of the language [1] is much larger than what we are concerned with here because many constructs in the language (e.g., variables, arbitrary events, floating-point types, delays) do nothave hardware equivalents and hence not synthesizable. Instead, we focus here on a particular dialect of VHDL dictated in part by the IEEE standard defining RTL synthesis [2]. Even within thisstandard, there are many equivalent ways to do essentially the same thing (e.g., define a process representing edgesensitive logic). This document presents a particular idiom that works; it does not try todefine all possible synthesizable VHDL specifications.

1 Structure
Much like a C program is mainly a series of function definitions, a VHDL specification is mainly a series of entity/architecturedefinition pairs. An entity is an object with a series of input and output ports that represent wires or busses, and an architecture is the “guts” of an entity, comprising concurrent assignment statements,processes, or instantiations of other entities. Concurrent assignment statements that use logical expressions to define the values of signals are one of the most common things in architectures. V HDLsupports the logical operators and, or, nand, nor, xnor, xnor, and not.
library ieee; use ieee.std_logic_1164.all; entity full_adder is port(a, b, c : in std_ulogic; sum, carry : out std_ulogic); endfull_adder; architecture imp of full_adder is begin sum B(0), c => ’0’, sum => C(0), carry => carry); bit1 : full_adder port map ( a => A(1), b => B(1), c => carry, sum => C(1), carry => C(2)); end...
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