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CD54HC4017, CD74HC4017
Data sheet acquired from Harris Semiconductor SCHS200D

November 1997 - Revised October 2003

High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs
Description
The ’HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to hightransition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes from high to low, and can be used in conjunction with the CLOCK ENABLE (CE) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except “0”, low. The device candrive up to 10 low power Schottky equivalent loads.

Features
• Fully Static Operation

[ /Title (CD74 HC401 7) /Subject (High Speed CMOS Logic Decade Counte

• Buffered Inputs • Common Reset • Positive Edge Clocking • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs. . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

Ordering Information
PART NUMBER CD54HC4017F3A CD74HC4017E CD74HC4017M CD74HC4017MT CD74HC4017M96CD74HC4017NSR CD74HC4017PW CD74HC4017PWR TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld SOP 16 Ld TSSOP 16 Ld TSSOP

NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250.

PinoutCD54HC4017 (CERDIP) CD74HC4017 (PDIP, SOIC, SOP, TSSOP) TOP VIEW
5 1 1 2 0 3 2 4 6 5 7 6 3 7 GND 8 16 VCC 15 MR 14 CP 13 CE 12 TC 11 9 10 4 9 8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

© 2003, Texas Instruments Incorporated

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CD54HC4017, CD74HC4017 Functional Diagram
3 14 CLOCK CLOCK 13 ENABLE 2 47 10 MASTER 15 RESET 1 5 6 9 11 12 0 1 2 3 4 5 6 7 8 9 TERMINAL COUNT DECODED DECIMAL OUT

TRUTH TABLE CP L X X ↑ ↓ X H CE X H X L X ↑ ↓ MR L L H L L L L OUTPUT STATE † No Change No Change “0” = H, “1”-”9” = L Increments Counter No Change No Change Increments Counter

H = High Level L = Low Level ↑ = High to Low Transition ↓ = Low to High Transition X = Don’t Care. † If n < 5 TC = H,Otherwise = L

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CD54HC4017, CD74HC4017
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Currentper Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA

Thermal Information
Package Thermal Impedance, θJA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC...
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